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b=AwbPJ7DnEwEF7JrWwccR7TPOCmHlGe/MYCfuMfZd2vfcMIt7fn+aUQdYJ02c5iPdY5jH BXpaWj0pfnwwCOE/gugHoO6MRlKUE7gKiYtyUT1WmTJ/OHrMZaA9AhGKZmzvYHiwfUBB 0GXJJ1+hrA8z1zYbJaKgWeH/KJM8GQCoujk/1XMOxr9R+jJPPFZWfLvJ8nirPwRkR8tV pXLPGtO1Y2/Q27TMP/TnttKrGTUuDtXBBE+rjSmi0Dvn04BdcoNTZoHs3y6pOa8bIDJ4 smh8R0UidDTxICDcLQSB51GEsR2ehkam6Sq3cAfgpexg7xQvxgxuwRusfgG6ZbtEUIwV ag== From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora Cc: , Subject: [PATCH v5 1/5] target/ppc: reduce code duplication across Power9/10 init code Date: Thu, 6 Jun 2024 17:46:53 +0530 Message-ID: <20240606121657.254308-2-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240606121657.254308-1-adityag@linux.ibm.com> References: <20240606121657.254308-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Mjelj1CWBtyegDbZPXZ3W3qn3wALygAd X-Proofpoint-GUID: GPGKtGbkx9U9L_DdEUoZXBI34LVQhsE5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-06_01,2024-06-06_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 suspectscore=0 phishscore=0 malwarescore=0 mlxscore=0 clxscore=1015 spamscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2406060090 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1717676308673100015 Content-Type: text/plain; charset="utf-8" From: Harsh Prateek Bora Power9/10 initialization code consists of a lot of logical OR of various flag bits as supported by respective Power platform during its initialization, most of which is duplicated and only selected bits are added or removed as needed with each new platform support being added. Remove the duplicate code and share using common macros. Signed-off-by: Harsh Prateek Bora --- target/ppc/cpu_init.c | 124 +++++------------------------------------- target/ppc/cpu_init.h | 78 ++++++++++++++++++++++++++ 2 files changed, 93 insertions(+), 109 deletions(-) create mode 100644 target/ppc/cpu_init.h diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 01e358a4a5ac..3d8a112935ae 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -51,6 +51,7 @@ #include "kvm_ppc.h" #endif =20 +#include "cpu_init.h" /* #define PPC_DEBUG_SPR */ /* #define USE_APPLE_GDB */ =20 @@ -6508,58 +6509,15 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) dc->fw_name =3D "PowerPC,POWER9"; dc->desc =3D "POWER9"; pcc->pvr_match =3D ppc_pvr_match_power9; - pcc->pcr_mask =3D PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; - pcc->pcr_supported =3D PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_= 2_06 | - PCR_COMPAT_2_05; + pcc->pcr_mask =3D POWERPC_POWER9_PCC_PCR_MASK; + pcc->pcr_supported =3D POWERPC_POWER9_PCC_PCR_SUPPORTED; pcc->init_proc =3D init_proc_POWER9; pcc->check_pow =3D check_pow_nocheck; pcc->check_attn =3D check_attn_hid0_power9; - pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWS= YNC | - PPC2_BCDA_ISA206; - pcc->msr_mask =3D (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_TM) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask =3D LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + pcc->insns_flags =3D POWERPC_FAMILY_POWER9_INSNS_FLAGS; + pcc->insns_flags2 =3D POWERPC_FAMILY_POWER9_INSNS_FLAGS2; + pcc->msr_mask =3D POWERPC_POWER9_PCC_MSR_MASK; + pcc->lpcr_mask =3D POWERPC_POWER9_PCC_LPCR_MASK; pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; #if !defined(CONFIG_USER_ONLY) @@ -6572,10 +6530,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->excp_model =3D POWERPC_EXCP_POWER9; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; - pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; + pcc->flags =3D POWERPC_POWER9_PCC_FLAGS; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; } @@ -6688,60 +6643,15 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) dc->fw_name =3D "PowerPC,POWER10"; dc->desc =3D "POWER10"; pcc->pvr_match =3D ppc_pvr_match_power10; - pcc->pcr_mask =3D PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | - PCR_COMPAT_3_00; - pcc->pcr_supported =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_= 2_07 | - PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->pcr_mask =3D POWERPC_POWER10_PCC_PCR_MASK; + pcc->pcr_supported =3D POWERPC_POWER10_PCC_PCR_SUPPORTED; pcc->init_proc =3D init_proc_POWER10; pcc->check_pow =3D check_pow_nocheck; pcc->check_attn =3D check_attn_hid0_power9; - pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | - PPC_FLOAT_FRSQRTES | - PPC_FLOAT_STFIWX | - PPC_FLOAT_EXT | - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | - PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD | - PPC_CILDST; - pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | - PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | - PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | - PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | - PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | - PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; - pcc->msr_mask =3D (1ull << MSR_SF) | - (1ull << MSR_HV) | - (1ull << MSR_VR) | - (1ull << MSR_VSX) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_FP) | - (1ull << MSR_ME) | - (1ull << MSR_FE0) | - (1ull << MSR_SE) | - (1ull << MSR_DE) | - (1ull << MSR_FE1) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_PMM) | - (1ull << MSR_RI) | - (1ull << MSR_LE); - pcc->lpcr_mask =3D LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | - (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | - LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | - (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | - LPCR_DEE | LPCR_OEE)) - | LPCR_MER | LPCR_GTSE | LPCR_TC | - LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; - /* DD2 adds an extra HAIL bit */ - pcc->lpcr_mask |=3D LPCR_HAIL; + pcc->insns_flags =3D POWERPC_FAMILY_POWER9_INSNS_FLAGS; /* same as P9 = */ + pcc->insns_flags2 =3D POWERPC_FAMILY_POWER10_INSNS_FLAGS2; + pcc->msr_mask =3D POWERPC_POWER10_PCC_MSR_MASK; + pcc->lpcr_mask =3D POWERPC_POWER10_PCC_LPCR_MASK; =20 pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; pcc->mmu_model =3D POWERPC_MMU_3_00; @@ -6754,11 +6664,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->excp_model =3D POWERPC_EXCP_POWER10; pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; - pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | - POWERPC_FLAG_BE | POWERPC_FLAG_PMM | - POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_SCV | - POWERPC_FLAG_BHRB; + pcc->flags =3D POWERPC_POWER10_PCC_FLAGS; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; } diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h new file mode 100644 index 000000000000..e04be6a655d8 --- /dev/null +++ b/target/ppc/cpu_init.h @@ -0,0 +1,78 @@ +#ifndef TARGET_PPC_CPU_INIT_H +#define TARGET_PPC_CPU_INIT_H + +#define POWERPC_FAMILY_POWER9_INSNS_FLAGS \ + PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | \ + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES | \ + PPC_FLOAT_STFIWX | PPC_FLOAT_EXT |PPC_CACHE | PPC_CACHE_ICBI | \ + PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \ + PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | \ + PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD | \ + PPC_CILDST + +#define POWERPC_FAMILY_POWER9_INSNS_FLAGS2_COMMON \ + PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | \ + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ + PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | \ + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | \ + PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \ + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206 + +#define POWERPC_FAMILY_POWER9_INSNS_FLAGS2 \ + POWERPC_FAMILY_POWER9_INSNS_FLAGS2_COMMON | PPC2_TM +#define POWERPC_FAMILY_POWER10_INSNS_FLAGS2 \ + POWERPC_FAMILY_POWER9_INSNS_FLAGS2_COMMON | PPC2_ISA310 + +#define POWERPC_POWER9_COMMON_PCC_MSR_MASK \ + (1ull << MSR_SF) | \ + (1ull << MSR_HV) | \ + (1ull << MSR_VR) | \ + (1ull << MSR_VSX) | \ + (1ull << MSR_EE) | \ + (1ull << MSR_PR) | \ + (1ull << MSR_FP) | \ + (1ull << MSR_ME) | \ + (1ull << MSR_FE0) | \ + (1ull << MSR_SE) | \ + (1ull << MSR_DE) | \ + (1ull << MSR_FE1) | \ + (1ull << MSR_IR) | \ + (1ull << MSR_DR) | \ + (1ull << MSR_PMM) | \ + (1ull << MSR_RI) | \ + (1ull << MSR_LE) + +#define POWERPC_POWER9_PCC_MSR_MASK \ + POWERPC_POWER9_COMMON_PCC_MSR_MASK | (1ull << MSR_TM) +#define POWERPC_POWER10_PCC_MSR_MASK \ + POWERPC_POWER9_COMMON_PCC_MSR_MASK +#define POWERPC_POWER9_PCC_PCR_MASK \ + PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 +#define POWERPC_POWER10_PCC_PCR_MASK \ + POWERPC_POWER9_PCC_PCR_MASK | PCR_COMPAT_3_00 +#define POWERPC_POWER9_PCC_PCR_SUPPORTED \ + PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05 +#define POWERPC_POWER10_PCC_PCR_SUPPORTED \ + POWERPC_POWER9_PCC_PCR_SUPPORTED | PCR_COMPAT_3_10 +#define POWERPC_POWER9_PCC_LPCR_MASK = \ + LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | = \ + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | = \ + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | = \ + (LPCR_PECE_L_MASK & (LPCR_PDEE|LPCR_HDEE|LPCR_EEE|LPCR_DEE|LPCR_OEE)) = | \ + LPCR_MER | LPCR_GTSE | LPCR_TC | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE |= \ + LPCR_HDICE +/* DD2 adds an extra HAIL bit */ +#define POWERPC_POWER10_PCC_LPCR_MASK \ + POWERPC_POWER9_PCC_LPCR_MASK | LPCR_HAIL +#define POWERPC_POWER9_PCC_FLAGS_COMMON \ + POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | \ + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | \ + POWERPC_FLAG_VSX | POWERPC_FLAG_SCV + +#define POWERPC_POWER9_PCC_FLAGS \ + POWERPC_POWER9_PCC_FLAGS_COMMON | POWERPC_FLAG_TM +#define POWERPC_POWER10_PCC_FLAGS \ + POWERPC_POWER9_PCC_FLAGS_COMMON | POWERPC_FLAG_BHRB + +#endif /* TARGET_PPC_CPU_INIT_H */ --=20 2.45.1 From nobody Mon Nov 25 02:50:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1717676306734100009 Add CPU target code to add support for new Power11 Processor. Power11 core is same as Power10, hence reuse functions defined for Power10. Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Harsh Prateek Bora Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Signed-off-by: Aditya Gupta --- target/ppc/compat.c | 7 ++++++ target/ppc/cpu-models.c | 3 +++ target/ppc/cpu-models.h | 3 +++ target/ppc/cpu_init.c | 54 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 67 insertions(+) diff --git a/target/ppc/compat.c b/target/ppc/compat.c index ebef2cccecf3..12dd8ae290ca 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] =3D { .pcr_level =3D PCR_COMPAT_3_10, .max_vthreads =3D 8, }, + { /* POWER11, ISA3.10 */ + .name =3D "power11", + .pvr =3D CPU_POWERPC_LOGICAL_3_10_PLUS, + .pcr =3D PCR_COMPAT_3_10, + .pcr_level =3D PCR_COMPAT_3_10, + .max_vthreads =3D 8, + }, }; =20 static const CompatInfo *compat_by_pvr(uint32_t pvr) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index f2301b43f78b..ece348178188 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -734,6 +734,8 @@ "POWER9 v2.2") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER= 10, "POWER10 v2.0") + POWERPC_DEF("power11_v2.0", CPU_POWERPC_POWER11_DD20, POWER= 11, + "POWER11_v2.0") #endif /* defined (TARGET_PPC64) */ =20 /*************************************************************************= **/ @@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] =3D { { "power8nvl", "power8nvl_v1.0" }, { "power9", "power9_v2.2" }, { "power10", "power10_v2.0" }, + { "power11", "power11_v2.0" }, #endif =20 /* Generic PowerPCs */ diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0229ef3a9a5c..ef74e387b047 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -354,6 +354,8 @@ enum { CPU_POWERPC_POWER10_BASE =3D 0x00800000, CPU_POWERPC_POWER10_DD1 =3D 0x00801100, CPU_POWERPC_POWER10_DD20 =3D 0x00801200, + CPU_POWERPC_POWER11_BASE =3D 0x00820000, + CPU_POWERPC_POWER11_DD20 =3D 0x00821200, CPU_POWERPC_970_v22 =3D 0x00390202, CPU_POWERPC_970FX_v10 =3D 0x00391100, CPU_POWERPC_970FX_v20 =3D 0x003C0200, @@ -391,6 +393,7 @@ enum { CPU_POWERPC_LOGICAL_2_07 =3D 0x0F000004, CPU_POWERPC_LOGICAL_3_00 =3D 0x0F000005, CPU_POWERPC_LOGICAL_3_10 =3D 0x0F000006, + CPU_POWERPC_LOGICAL_3_10_PLUS =3D 0x0F000007, }; =20 /* System version register (used on MPC 8xxx) = */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3d8a112935ae..9aa098935d05 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6669,6 +6669,60 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->l1_icache_size =3D 0x8000; } =20 +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool= best) +{ + uint32_t base =3D pvr & CPU_POWERPC_POWER_SERVER_MASK; + uint32_t pcc_base =3D pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; + + if (!best && (base =3D=3D CPU_POWERPC_POWER11_BASE)) { + return true; + } + + if (base !=3D pcc_base) { + return false; + } + + if ((pvr & 0x0f00) =3D=3D (pcc->pvr & 0x0f00)) { + return true; + } + + return false; +} + +POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->fw_name =3D "PowerPC,POWER11"; + dc->desc =3D "POWER11"; + pcc->pvr_match =3D ppc_pvr_match_power11; + pcc->pcr_mask =3D POWERPC_POWER10_PCC_PCR_MASK; + pcc->pcr_supported =3D POWERPC_POWER10_PCC_PCR_SUPPORTED; + pcc->init_proc =3D init_proc_POWER10; + pcc->check_pow =3D check_pow_nocheck; + pcc->check_attn =3D check_attn_hid0_power9; + pcc->insns_flags =3D POWERPC_FAMILY_POWER9_INSNS_FLAGS; /* same as P9 = */ + pcc->insns_flags2 =3D POWERPC_FAMILY_POWER10_INSNS_FLAGS2; + pcc->msr_mask =3D POWERPC_POWER10_PCC_MSR_MASK; + pcc->lpcr_mask =3D POWERPC_POWER10_PCC_LPCR_MASK; + + pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; + pcc->mmu_model =3D POWERPC_MMU_3_00; +#if !defined(CONFIG_USER_ONLY) + /* segment page size remain the same */ + pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; + pcc->radix_page_info =3D &POWER10_radix_page_info; + pcc->lrg_decr_bits =3D 56; +#endif + pcc->excp_model =3D POWERPC_EXCP_POWER10; + pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach =3D bfd_mach_ppc64; + pcc->flags =3D POWERPC_POWER10_PCC_FLAGS; + pcc->l1_dcache_size =3D 0x8000; + pcc->l1_icache_size =3D 0x8000; +} + #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { --=20 2.45.1 From nobody Mon Nov 25 02:50:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1717676323; cv=none; d=zohomail.com; s=zohoarc; b=d5SxfJh8RjMzW41SVzVcK/HokKwsrqng7pUP7jqFivIf3WIOFGWwdlF4gTRDJglU1fRUKekmMcbycFM7ZTnlnMVT94kZ18Gwaq44PP5exPA2YY6DsYV8oodXzk2Uf0PDuh82ATcstSzpaCykDnqrv69N6/NpOTCI4RrR4p6QjEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717676323; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: JUMbZq8y6szL_FCYZnKmTlst3FdsqitY X-Proofpoint-ORIG-GUID: AKzAYABMQYUOAhSY43omVkp_HNhCvfAu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-06_01,2024-06-06_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 impostorscore=0 mlxlogscore=933 spamscore=0 bulkscore=0 adultscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2406060090 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1717676324764100004 Add sPAPR CPU Core definition for Power11 Cc: David Gibson (reviewer:sPAPR (pseries)) Cc: Harsh Prateek Bora (reviewer:sPAPR (pseries)) Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Harsh Prateek Bora Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Harsh Prateek Bora Signed-off-by: Aditya Gupta --- docs/system/ppc/pseries.rst | 17 +++++++++++++---- hw/ppc/spapr_cpu_core.c | 1 + 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst index a876d897b6e4..bbc51aa7fcdb 100644 --- a/docs/system/ppc/pseries.rst +++ b/docs/system/ppc/pseries.rst @@ -14,10 +14,19 @@ virtualization capabilities. Supported devices =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 - * Multi processor support for many Power processors generations: POWER7, - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ ex= ists, - but its state is unknown. - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) + * Multi processor support for many Power processors generations: + - POWER7, POWER7+ + - POWER8, POWER8NVL + - POWER9 + - Power10 + - Power11 + - Support for POWER5+ also exists, works with correct kernel/userspace + * Interrupt Controller + - XICS (POWER8) + - XIVE (Supported by below:) + - POWER9 + - Power10 + - Power11 * vPHB PCIe Host bridge. * vscsi and vnet devices, compatible with the same devices available on a PowerVM hypervisor with VIOS managing LPARs. diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index e7c9edd033c8..62416b7e0a7e 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] =3D { DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"), DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"), DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"), + DEFINE_SPAPR_CPU_CORE_TYPE("power11_v2.0"), #ifdef CONFIG_KVM DEFINE_SPAPR_CPU_CORE_TYPE("host"), #endif --=20 2.45.1 From nobody Mon Nov 25 02:50:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=Ss59u9TjusRJmOp0+mWHBLXM62IL/ME+k/NxPOYI6FA=; b=eTAL6amw1GVUGofVfePznawxrb5ZEIa7HW3VIHr+qyp3MryRLTD/UzXTEonmD9XeNtiA 0YzySmt3wwAPOdxXMvy4uZXCuBJxxtcizfS8MoeA3ug6WeLcABx2NkqqgZZAh2vqhOFw jXjv0mYrgtO5hbFBI+4vNQLf5/v0BHGSnhSfuj7siD4Wa0WxdH9J/rFm6N+pncjgnHQb J24M8y+QNYKhcEbwo2d6Wy+MMHnm+wPwREqK+udOrzgdCosP4aQ+LJmfBrg13nZWXonB 7lZ09X6HdCt9MsIt2bq3+eWPoqKUZH/XVev0XTNcJbUKcwdFvIO1XNpJHtQV18ax3zxn hw== From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora Cc: , , Daniel Henrique Barboza Subject: [PATCH v5 4/5] target/ppc: Introduce 'PowerPCCPUClass::logical_pvr' Date: Thu, 6 Jun 2024 17:46:56 +0530 Message-ID: <20240606121657.254308-5-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240606121657.254308-1-adityag@linux.ibm.com> References: <20240606121657.254308-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 0egZtOh931k92n4HTwvBX7y_96rjV7gO X-Proofpoint-ORIG-GUID: yXryiMW96zrVSskQKC8aZt426mvUCHtL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-06_01,2024-06-06_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 mlxscore=0 suspectscore=0 bulkscore=0 spamscore=0 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2406060090 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1717676324713100003 Introduce 'PnvChipClass::logical_pvr' to know corresponding logical PVR of a PowerPC CPU. This helps to have a one-to-one mapping between PVR and logical PVR for a CPU, and used in a later commit to handle cases where PCR of two generations of Power chip is same, which causes regressions with compat-mod= e. Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: Harsh Prateek Bora Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Signed-off-by: Aditya Gupta --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2015e603d4e0..ff43e3645228 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1504,6 +1504,7 @@ struct PowerPCCPUClass { void (*parent_parse_features)(const char *type, char *str, Error **err= p); =20 uint32_t pvr; + uint32_t logical_pvr; /* * If @best is false, match if pcc is in the family of pvr * Else match only if pcc is the best match for pvr in this family. diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 9aa098935d05..50f136cca7f0 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6152,6 +6152,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) =20 dc->fw_name =3D "PowerPC,POWER7"; dc->desc =3D "POWER7"; + pcc->logical_pvr =3D CPU_POWERPC_LOGICAL_2_06_PLUS; pcc->pvr_match =3D ppc_pvr_match_power7; pcc->pcr_mask =3D PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; pcc->pcr_supported =3D PCR_COMPAT_2_06 | PCR_COMPAT_2_05; @@ -6315,6 +6316,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) =20 dc->fw_name =3D "PowerPC,POWER8"; dc->desc =3D "POWER8"; + pcc->logical_pvr =3D CPU_POWERPC_LOGICAL_2_07; pcc->pvr_match =3D ppc_pvr_match_power8; pcc->pcr_mask =3D PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->pcr_supported =3D PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_= 2_05; @@ -6508,6 +6510,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) =20 dc->fw_name =3D "PowerPC,POWER9"; dc->desc =3D "POWER9"; + pcc->logical_pvr =3D CPU_POWERPC_LOGICAL_3_00; pcc->pvr_match =3D ppc_pvr_match_power9; pcc->pcr_mask =3D POWERPC_POWER9_PCC_PCR_MASK; pcc->pcr_supported =3D POWERPC_POWER9_PCC_PCR_SUPPORTED; @@ -6642,6 +6645,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) =20 dc->fw_name =3D "PowerPC,POWER10"; dc->desc =3D "POWER10"; + pcc->logical_pvr =3D CPU_POWERPC_LOGICAL_3_10; pcc->pvr_match =3D ppc_pvr_match_power10; pcc->pcr_mask =3D POWERPC_POWER10_PCC_PCR_MASK; pcc->pcr_supported =3D POWERPC_POWER10_PCC_PCR_SUPPORTED; @@ -6696,6 +6700,7 @@ POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) =20 dc->fw_name =3D "PowerPC,POWER11"; dc->desc =3D "POWER11"; + pcc->logical_pvr =3D CPU_POWERPC_LOGICAL_3_10_PLUS; pcc->pvr_match =3D ppc_pvr_match_power11; pcc->pcr_mask =3D POWERPC_POWER10_PCC_PCR_MASK; pcc->pcr_supported =3D POWERPC_POWER10_PCC_PCR_SUPPORTED; --=20 2.45.1 From nobody Mon Nov 25 02:50:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1717676304; cv=none; d=zohomail.com; s=zohoarc; b=Akph9ptr6if1PKucvBSoPSeDCIzOSIoTeFyYWms1HfUMvslJWtd7RV8CACyxGdeYjtwtsHTMcPK+ehy27sZdRKPYOzXt51u49ZMAWXy144IBYh0gzp0OQgPm4+VKGIUXd0l96Z8LQqY2OqgSl01yZ7wohP9+dmORPuvpc4+cQng= ARC-Message-Signature: i=1; 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Thu, 6 Jun 2024 12:17:10 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc : content-transfer-encoding : content-type : date : from : in-reply-to : message-id : mime-version : references : subject : to; s=pp1; bh=h6VHakey/41eoMID9x1GF+gfi2vVsl+KAyfGGnlm/fw=; b=iIXwP883VigMmLr//zRMcK/0fXFV9111DucnE5563TWgN/pZMMmsN6lJZe4rUq0TdzgT WgJaCCBQ72aQ4+kLtYldleKIG2FPsUvq66eQJF/eXTmPMN7V9hqZvOgWdYIW+zZi1C7q S0Fq35nWzbWeJI1pMXi+JdxYF79X9hch+nKjX77HDAwTVqXPMWqJP9YAJmSr/dVRMh4r UCB0VNfaRhC0Dk6prgpEpL8HRGRUGLtJvGlEewyqDxG64MOuNihfWZHUzjOjpYf9NnBu IFMu8XkfWS/ULFfS3DWhQEgF8zpnvZ9YVb2unr/w6tVkIxJ+odFpnhN1YyD1PoZRfntz wg== From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora Cc: , , Daniel Henrique Barboza Subject: [PATCH v5 5/5] target/ppc: Fix regression due to Power10 and Power11 having same PCR Date: Thu, 6 Jun 2024 17:46:57 +0530 Message-ID: <20240606121657.254308-6-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240606121657.254308-1-adityag@linux.ibm.com> References: <20240606121657.254308-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: AjQWrj9Rpqfj1Avuo6WORNhxMb2v9vvy X-Proofpoint-ORIG-GUID: MU3k9KJD9dIb87hgU2Mkt8djb_OU3NQw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-06_01,2024-06-06_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 impostorscore=0 mlxlogscore=884 spamscore=0 bulkscore=0 adultscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2406060090 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1717676306706100007 Power11 has the same PCR (Processor Compatibility Register) value, as Power10. Due to this, QEMU considers Power11 as a valid compat-mode for Power10, ie. earlier it was possible to run QEMU with '-M pseries,max-compat-mode=3D= power11 --cpu power10' Same PCR also introduced a regression where `-M pseries --cpu power10` boots as Power11 (ie. logical PVR is of Power11, even though PVR is Power10= ). The regression was due to 'do_client_architecture_support' checking for valid compat modes and finding Power11 to be a valid compat mode for Power10 (it happens even without passing 'max-compat-mode' explicitly). Fix compat-mode issue and regression, by ensuring a future Power processor (with a higher logical_pvr value, eg. P11) cannot be valid compat-mode for an older Power processor (eg. P10) Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: Harsh Prateek Bora Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Signed-off-by: Aditya Gupta --- target/ppc/compat.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/compat.c b/target/ppc/compat.c index 12dd8ae290ca..168a3c06316f 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -139,6 +139,10 @@ static bool pcc_compat(PowerPCCPUClass *pcc, uint32_t = compat_pvr, /* Outside specified range */ return false; } + if (compat->pvr > pcc->logical_pvr) { + /* Older CPU cannot support a newer processor's compat mode */ + return false; + } if (!(pcc->pcr_supported & compat->pcr_level)) { /* Not supported by this CPU */ return false; --=20 2.45.1