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([71.212.132.216]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c28066d511sm1720915a91.9.2024.06.05.10.23.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 10:23:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717608183; x=1718212983; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=XV0zqgdiizZid+l8CktjOn6UyrHM7Afq3vRi3rtAjaU=; b=GenLpGoUh3PzHwnPqSHZfYIsmYGpZIkpUtCnHXXkr/RsHmBHPEKGWY9AIxhEeTBP2P zQJ1MW4GKY8RYIKHMd0dzup3GCIvzmAnyLGw5y6uOTlacGU0YoToG/gqPvdW5z8GsHbF 1GFxoczKwoAPd4HM7q+rAUooQbfOCtKFSxWnff9g3WtJyPZ9W/6HwfVKww7hFQ2WoPd/ x5CimT2Y3WbVn0I6mOwaEzdQPDcpw9Uwm9TkbLu/O4gIuT48EQcX3B/kce3AqoaWVuXW 7yNxuRadiYTwHD8tL7qUljybdjLUi8vI3QzCcLU3fcQ9lJsIqvI/PbzsQNEuOyVuIqHz ZPcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717608183; x=1718212983; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XV0zqgdiizZid+l8CktjOn6UyrHM7Afq3vRi3rtAjaU=; b=QLhQMghj9Ay60Bx4BAFpaareJbydNauXGOx3UVqa2ZOJJ6ieuXoX/l1WzvD9DnXRLL eMjEJH2Z9EvnRM3JiNQSXhj+vE7ru50yuqO3F6ZNKOzTbQM49wE3sc16lLdBiijIJSqG KAeMpm3D5KH38nGGNFU+HQw9nOD5crTXcObJo0NBISwUkWy9atOaMMv2QtNp2udrAhbS +fCI9ag3XlFB6v5sDdhciH8q8++xCUtjAVlgCRagEf5aaGNR5seCQWDYh/aEFswgX7Od pUMj/zq+mMw+bttkbw+O0CD3QxZjoH7zcGNSZx3VH5MZFKYk5e1eMUSOBx3FNGrXripX XCSQ== X-Gm-Message-State: AOJu0YxWXZWOm2csE8sDGTwFS9c/xnIPUIm204D1nXS4e2KyTPm0WrrL hKP6aZkQbGBeLH8wC2HS2rdjjTvnM1QZ91boIGZvrDq7HmwP/bjZAUFHj8tBD1k7nwXzE1Iy6gL N X-Google-Smtp-Source: AGHT+IGgLV96gLJU3jSuZCs6iYYdyv0FfCXW3GXgow3jo+cPQI7Y6N4bsJD7FooK99/gPWBlpLRDRw== X-Received: by 2002:a17:90b:1984:b0:2c2:344:281b with SMTP id 98e67ed59e1d1-2c299a22dc4mr386729a91.17.1717608182786; Wed, 05 Jun 2024 10:23:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 08/38] target/sparc: Remove cpu_fpr[] Date: Wed, 5 Jun 2024 10:22:23 -0700 Message-Id: <20240605172253.356302-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605172253.356302-1-richard.henderson@linaro.org> References: <20240605172253.356302-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1717608377352100005 Content-Type: text/plain; charset="utf-8" Use explicit loads and stores to env instead. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 158 +++++++++++++++++++++------------------ 1 file changed, 84 insertions(+), 74 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 750a3e6554..362e88de18 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -123,8 +123,7 @@ static TCGv cpu_gsr; #define cpu_xcc_C ({ qemu_build_not_reached(); NULL; }) #endif =20 -/* Floating point registers */ -static TCGv_i64 cpu_fpr[TARGET_DPREGS]; +/* Floating point comparison registers */ static TCGv_i32 cpu_fcc[TARGET_FCCREGS]; =20 #define env_field_offsetof(X) offsetof(CPUSPARCState, X) @@ -209,50 +208,72 @@ static void gen_update_fprs_dirty(DisasContext *dc, i= nt rd) } =20 /* floating point registers moves */ + +static int gen_offset_fpr_F(unsigned int reg) +{ + int ret; + + tcg_debug_assert(reg < 32); + ret=3D offsetof(CPUSPARCState, fpr[reg / 2]); + if (reg & 1) { + ret +=3D offsetof(CPU_DoubleU, l.lower); + } else { + ret +=3D offsetof(CPU_DoubleU, l.upper); + } + return ret; +} + static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) { TCGv_i32 ret =3D tcg_temp_new_i32(); - if (src & 1) { - tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]); - } else { - tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]); - } + tcg_gen_ld_i32(ret, tcg_env, gen_offset_fpr_F(src)); return ret; } =20 static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) { - TCGv_i64 t =3D tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(t, v); - tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t, - (dst & 1 ? 0 : 32), 32); + tcg_gen_st_i32(v, tcg_env, gen_offset_fpr_F(dst)); gen_update_fprs_dirty(dc, dst); } =20 +static int gen_offset_fpr_D(unsigned int reg) +{ + tcg_debug_assert(reg < 64); + tcg_debug_assert(reg % 2 =3D=3D 0); + return offsetof(CPUSPARCState, fpr[reg / 2]); +} + static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) { - return cpu_fpr[src / 2]; + TCGv_i64 ret =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(ret, tcg_env, gen_offset_fpr_D(src)); + return ret; } =20 static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v) { - tcg_gen_mov_i64(cpu_fpr[dst / 2], v); + tcg_gen_st_i64(v, tcg_env, gen_offset_fpr_D(dst)); gen_update_fprs_dirty(dc, dst); } =20 static TCGv_i128 gen_load_fpr_Q(DisasContext *dc, unsigned int src) { TCGv_i128 ret =3D tcg_temp_new_i128(); + TCGv_i64 h =3D gen_load_fpr_D(dc, src); + TCGv_i64 l =3D gen_load_fpr_D(dc, src + 2); =20 - tcg_gen_concat_i64_i128(ret, cpu_fpr[src / 2 + 1], cpu_fpr[src / 2]); + tcg_gen_concat_i64_i128(ret, l, h); return ret; } =20 static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, TCGv_i128 = v) { - tcg_gen_extr_i128_i64(cpu_fpr[dst / 2 + 1], cpu_fpr[dst / 2], v); - gen_update_fprs_dirty(dc, dst); + TCGv_i64 h =3D tcg_temp_new_i64(); + TCGv_i64 l =3D tcg_temp_new_i64(); + + tcg_gen_extr_i128_i64(l, h, v); + gen_store_fpr_D(dc, dst, h); + gen_store_fpr_D(dc, dst + 2, l); } =20 /* moves */ @@ -1610,7 +1631,7 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, MemOp memop =3D da->memop; MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; - TCGv_i64 d64; + TCGv_i64 d64, l64; TCGv addr_tmp; =20 /* TODO: Use 128-bit load/store below. */ @@ -1632,16 +1653,20 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI = *da, MemOp orig_size, break; =20 case MO_64: - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop); + d64 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop); + gen_store_fpr_D(dc, rd, d64); break; =20 case MO_128: d64 =3D tcg_temp_new_i64(); + l64 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop); addr_tmp =3D tcg_temp_new(); tcg_gen_addi_tl(addr_tmp, addr, 8); - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx= , memop); - tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); + tcg_gen_qemu_ld_i64(l64, addr_tmp, da->mem_idx, memop); + gen_store_fpr_D(dc, rd, d64); + gen_store_fpr_D(dc, rd + 2, l64); break; default: g_assert_not_reached(); @@ -1653,9 +1678,11 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *= da, MemOp orig_size, if (orig_size =3D=3D MO_64 && (rd & 7) =3D=3D 0) { /* The first operation checks required alignment. */ addr_tmp =3D tcg_temp_new(); + d64 =3D tcg_temp_new_i64(); for (int i =3D 0; ; ++i) { - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); + gen_store_fpr_D(dc, rd + 2 * i, d64); if (i =3D=3D 7) { break; } @@ -1670,8 +1697,9 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, case GET_ASI_SHORT: /* Valid for lddfa only. */ if (orig_size =3D=3D MO_64) { - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, - memop | MO_ALIGN); + d64 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop | MO_ALIGN); + gen_store_fpr_D(dc, rd, d64); } else { gen_exception(dc, TT_ILL_INSN); } @@ -1696,17 +1724,19 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI = *da, MemOp orig_size, gen_store_fpr_F(dc, rd, d32); break; case MO_64: - gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, - r_asi, r_mop); + d64 =3D tcg_temp_new_i64(); + gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); + gen_store_fpr_D(dc, rd, d64); break; case MO_128: d64 =3D tcg_temp_new_i64(); + l64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); addr_tmp =3D tcg_temp_new(); tcg_gen_addi_tl(addr_tmp, addr, 8); - gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr_tmp, - r_asi, r_mop); - tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); + gen_helper_ld_asi(l64, tcg_env, addr_tmp, r_asi, r_mop); + gen_store_fpr_D(dc, rd, d64); + gen_store_fpr_D(dc, rd + 2, l64); break; default: g_assert_not_reached(); @@ -1722,6 +1752,7 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, MemOp memop =3D da->memop; MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; + TCGv_i64 d64; TCGv addr_tmp; =20 /* TODO: Use 128-bit load/store below. */ @@ -1741,8 +1772,8 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, tcg_gen_qemu_st_i32(d32, addr, da->mem_idx, memop | MO_ALIGN); break; case MO_64: - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, - memop | MO_ALIGN_4); + d64 =3D gen_load_fpr_D(dc, rd); + tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | MO_ALIGN_4= ); break; case MO_128: /* Only 4-byte alignment required. However, it is legal for t= he @@ -1750,11 +1781,12 @@ static void gen_stf_asi(DisasContext *dc, DisasASI = *da, MemOp orig_size, required to fix it up. Requiring 16-byte alignment here av= oids having to probe the second page before performing the first write. */ - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, - memop | MO_ALIGN_16); + d64 =3D gen_load_fpr_D(dc, rd); + tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | MO_ALIGN_1= 6); addr_tmp =3D tcg_temp_new(); tcg_gen_addi_tl(addr_tmp, addr, 8); - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx= , memop); + d64 =3D gen_load_fpr_D(dc, rd + 2); + tcg_gen_qemu_st_i64(d64, addr_tmp, da->mem_idx, memop); break; default: g_assert_not_reached(); @@ -1767,7 +1799,8 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, /* The first operation checks required alignment. */ addr_tmp =3D tcg_temp_new(); for (int i =3D 0; ; ++i) { - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + d64 =3D gen_load_fpr_D(dc, rd + 2 * i); + tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); if (i =3D=3D 7) { break; @@ -1783,8 +1816,8 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, case GET_ASI_SHORT: /* Valid for stdfa only. */ if (orig_size =3D=3D MO_64) { - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, - memop | MO_ALIGN); + d64 =3D gen_load_fpr_D(dc, rd); + tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2029,13 +2062,17 @@ static void gen_fmovq(DisasContext *dc, DisasCompar= e *cmp, int rd, int rs) { #ifdef TARGET_SPARC64 TCGv c2 =3D tcg_constant_tl(cmp->c2); + TCGv_i64 h =3D tcg_temp_new_i64(); + TCGv_i64 l =3D tcg_temp_new_i64(); =20 - tcg_gen_movcond_i64(cmp->cond, cpu_fpr[rd / 2], cmp->c1, c2, - cpu_fpr[rs / 2], cpu_fpr[rd / 2]); - tcg_gen_movcond_i64(cmp->cond, cpu_fpr[rd / 2 + 1], cmp->c1, c2, - cpu_fpr[rs / 2 + 1], cpu_fpr[rd / 2 + 1]); - - gen_update_fprs_dirty(dc, rd); + tcg_gen_movcond_i64(cmp->cond, h, cmp->c1, c2, + gen_load_fpr_D(dc, rs), + gen_load_fpr_D(dc, rd)); + tcg_gen_movcond_i64(cmp->cond, l, cmp->c1, c2, + gen_load_fpr_D(dc, rs + 2), + gen_load_fpr_D(dc, rd + 2)); + gen_store_fpr_D(dc, rd, h); + gen_store_fpr_D(dc, rd + 2, l); #else qemu_build_not_reached(); #endif @@ -4211,39 +4248,24 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *= a, MemOp mop) TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL) TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ) =20 -static bool do_fc(DisasContext *dc, int rd, bool c) +static bool do_fc(DisasContext *dc, int rd, int32_t c) { - uint64_t mask; - if (gen_trap_ifnofpu(dc)) { return true; } - - if (rd & 1) { - mask =3D MAKE_64BIT_MASK(0, 32); - } else { - mask =3D MAKE_64BIT_MASK(32, 32); - } - if (c) { - tcg_gen_ori_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], mask); - } else { - tcg_gen_andi_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], ~mask); - } - gen_update_fprs_dirty(dc, rd); + gen_store_fpr_F(dc, rd, tcg_constant_i32(c)); return advance_pc(dc); } =20 TRANS(FZEROs, VIS1, do_fc, a->rd, 0) -TRANS(FONEs, VIS1, do_fc, a->rd, 1) +TRANS(FONEs, VIS1, do_fc, a->rd, -1) =20 static bool do_dc(DisasContext *dc, int rd, int64_t c) { if (gen_trap_ifnofpu(dc)) { return true; } - - tcg_gen_movi_i64(cpu_fpr[rd / 2], c); - gen_update_fprs_dirty(dc, rd); + gen_store_fpr_D(dc, rd, tcg_constant_i64(c)); return advance_pc(dc); } =20 @@ -5137,12 +5159,6 @@ void sparc_tcg_init(void) "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", }; - static const char fregnames[32][4] =3D { - "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14", - "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30", - "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", - "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", - }; =20 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[= ] =3D { #ifdef TARGET_SPARC64 @@ -5199,12 +5215,6 @@ void sparc_tcg_init(void) (i - 8) * sizeof(target_ulong), gregnames[i]); } - - for (i =3D 0; i < TARGET_DPREGS; i++) { - cpu_fpr[i] =3D tcg_global_mem_new_i64(tcg_env, - offsetof(CPUSPARCState, fpr[i]= ), - fregnames[i]); - } } =20 void sparc_restore_state_to_opc(CPUState *cs, --=20 2.34.1