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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1717608431421100004 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sparc/helper.h | 1 + target/sparc/insns.decode | 1 + target/sparc/translate.c | 32 ++++++++++++++++++++++++++++++++ target/sparc/vis_helper.c | 23 +++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 84435b0932..e59307efc2 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -110,6 +110,7 @@ DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i= 64, i64, i64) DEF_HELPER_FLAGS_2(cmask8, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(cmask16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(cmask32, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fchksm16, TCG_CALL_NO_RWG_SE, i64, i64, i64) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 8be808d065..18d068d2af 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -410,6 +410,7 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ PDIST 10 ..... 110110 ..... 0 0011 1110 ..... \ &r_r_r_r rd=3D%dfp_rd rs1=3D%dfp_rd rs2=3D%dfp_rs1 rs3=3D%= dfp_rs2 =20 + FCHKSM16 10 ..... 110110 ..... 0 0100 0100 ..... @d_d_d FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @d_d_d FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @d_d_d diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2b0a1f5a9a..b8ba8eea74 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -788,6 +788,37 @@ static void gen_op_fmuld8sux16(TCGv_i64 dst, TCGv_i32 = src1, TCGv_i32 src2) tcg_gen_concat_i32_i64(dst, t0, t1); } =20 +#ifdef TARGET_SPARC64 +static void gen_vec_fchksm16(unsigned vece, TCGv_vec dst, + TCGv_vec src1, TCGv_vec src2) +{ + TCGv_vec a =3D tcg_temp_new_vec_matching(dst); + TCGv_vec c =3D tcg_temp_new_vec_matching(dst); + + tcg_gen_add_vec(vece, a, src1, src2); + tcg_gen_cmp_vec(TCG_COND_LTU, vece, c, a, src1); + /* Vector cmp produces -1 for true, so subtract to add carry. */ + tcg_gen_sub_vec(vece, dst, a, c); +} + +static void gen_op_fchksm16(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { + INDEX_op_cmp_vec, INDEX_op_add_vec, INDEX_op_sub_vec, + }; + static const GVecGen3 op =3D { + .fni8 =3D gen_helper_fchksm16, + .fniv =3D gen_vec_fchksm16, + .opt_opc =3D vecop_list, + .vece =3D MO_16, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &op); +} +#else +#define gen_op_fchksm16 ({ qemu_build_not_reached(); NULL; }) +#endif + static void finishing_insn(DisasContext *dc) { /* @@ -4761,6 +4792,7 @@ TRANS(FPADD16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_g= vec_add) TRANS(FPADD32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_add) TRANS(FPSUB16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sub) TRANS(FPSUB32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sub) +TRANS(FCHKSM16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fchksm16) =20 static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 20baa4ff71..fa607375d2 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -389,3 +389,26 @@ uint64_t helper_cmask32(uint64_t gsr, uint64_t src) =20 return deposit64(gsr, 32, 32, mask); } + +static inline uint16_t do_fchksm16(uint16_t src1, uint16_t src2) +{ + uint16_t a =3D src1 + src2; + uint16_t c =3D a < src1; + return a + c; +} + +uint64_t helper_fchksm16(uint64_t src1, uint64_t src2) +{ + VIS64 r, s1, s2; + + s1.ll =3D src1; + s2.ll =3D src2; + r.ll =3D 0; + + r.VIS_W64(0) =3D do_fchksm16(s1.VIS_W64(0), s2.VIS_W64(0)); + r.VIS_W64(1) =3D do_fchksm16(s1.VIS_W64(1), s2.VIS_W64(1)); + r.VIS_W64(2) =3D do_fchksm16(s1.VIS_W64(2), s2.VIS_W64(2)); + r.VIS_W64(3) =3D do_fchksm16(s1.VIS_W64(3), s2.VIS_W64(3)); + + return r.ll; +} --=20 2.34.1