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[89.104.8.249]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a51023af4sm7111335a12.29.2024.06.05.04.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 04:26:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20230601.gappssmtp.com; s=20230601; t=1717586784; x=1718191584; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vyDhWiLePoGq4AfWFWJeqV8roAH5mNHGKlDLBH2osgY=; b=3Z8CET9pUBOUap+aFB/mH5TFdsssBWbKJ4suoAF9GulYBzyena9QPUYq+Fwv005h/8 LJW5uzRI/gmkkLTpZddK1F94/Ex1cggVgQ6sqjhhjH27+pNLLOlGDy9dat96UupXfHqM VEc15Hw9f0xUpy2SVOxLWWbdPyB2hslU8Vc54uTOaMfuUCf4DEp5VF+bBBqywOXTlQ+H 3UAtzVV6LVzEc57Jfif4at2E8HcqDTIfCUCmVgflS2wUlIo8H3zSBNa19mztvRpwmobk /wqLthEjhWL+oYvsqcDfL3t7Rq7oz5rLpjA+YiRB8wnKQET3qOecLycOeW6fObkW+v+T 1Utg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717586784; x=1718191584; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vyDhWiLePoGq4AfWFWJeqV8roAH5mNHGKlDLBH2osgY=; b=auT4ycXgZVnq8N0rk9O2vM3ISgRaU6wR2ENyG4y/2ftkp1GgB0oFIV8cbIR0jvM8lk lwXCumhr7pDSd/AjR+NkU3mR6PphZnS3Le0wdUqRwCMoVx3VVMuScb6nN0hK79Mosecc Xqk5BqlSTTrPNVWGfaJe2vgjpDpU5B+63tbbzdfkgDf0/ymZNoLDuPtxtABsXO+g8mN7 AOG85XmDN3VpovjEWcOHrTVygLsv8H/tWVGzSNE9NJFsRLecCNu77+A95kYcDzq5YacV 3Cdb4UosFllSbtd2XKpRFAYt8hOF57nzKgS54YdHjj40eCsjy/6TZI0BGqdlKOwSjFSA 4jWw== X-Gm-Message-State: AOJu0Yxyxy4epsW+PINRnsLklqjBKykaEaYKUA3DVnKn16nxqQM4oE/6 vrVofusxgU1N6wlCboK/QwfMTEYTjRx8iCzkJZRRyTLtwvoHuDNZufo614IQ0nbxXIrAhV4ecUU = X-Google-Smtp-Source: AGHT+IHXCCwvT2GAm9AVbE8F50YCR9Oy5xtPzt827/YfYl8DFe+hwOsbaiDvVfWSPaEBykjKyJfj+w== X-Received: by 2002:a50:cac7:0:b0:57a:7490:a872 with SMTP id 4fb4d7f45d1cf-57a8b6a9f9fmr1953528a12.10.1717586783841; Wed, 05 Jun 2024 04:26:23 -0700 (PDT) From: Phil Dennis-Jordan To: qemu-devel@nongnu.org Cc: dirty@apple.com, rbolshakov@ddn.com, lists@philjordan.eu, Phil Dennis-Jordan , Roman Bolshakov Subject: [PATCH v3 1/7] i386/hvf: Adds support for INVTSC cpuid bit Date: Wed, 5 Jun 2024 13:25:50 +0200 Message-Id: <20240605112556.43193-2-phil@philjordan.eu> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20240605112556.43193-1-phil@philjordan.eu> References: <20240605112556.43193-1-phil@philjordan.eu> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: neutral client-ip=2a00:1450:4864:20::632; envelope-from=phil@philjordan.eu; helo=mail-ej1-x632.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @philjordan-eu.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1717586908924100003 Content-Type: text/plain; charset="utf-8" This patch adds the INVTSC bit to the Hypervisor.framework accelerator's CPUID bit passthrough allow-list. Previously, specifying +invtsc in the CPU configuration would fail with the following warning despite the host CPU advertising the feature: qemu-system-x86_64: warning: host doesn't support requested feature: CPUID.80000007H:EDX.invtsc [bit 8] x86 macOS itself relies on a fixed rate TSC for its own Mach absolute time timestamp mechanism, so there's no reason we can't enable this bit for gues= ts. When the feature is enabled, a migration blocker is installed. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov --- target/i386/hvf/hvf.c | 18 ++++++++++++++++++ target/i386/hvf/x86_cpuid.c | 4 ++++ 2 files changed, 22 insertions(+) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index e493452acb..e6e916225b 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -49,6 +49,8 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/memalign.h" +#include "qapi/error.h" +#include "migration/blocker.h" =20 #include "sysemu/hvf.h" #include "sysemu/hvf_int.h" @@ -74,6 +76,8 @@ #include "qemu/accel.h" #include "target/i386/cpu.h" =20 +static Error *invtsc_mig_blocker; + void vmx_update_tpr(CPUState *cpu) { /* TODO: need integrate APIC handling */ @@ -221,6 +225,8 @@ int hvf_arch_init_vcpu(CPUState *cpu) { X86CPU *x86cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86cpu->env; + Error *local_err =3D NULL; + int r; uint64_t reqCap; =20 init_emu(); @@ -238,6 +244,18 @@ int hvf_arch_init_vcpu(CPUState *cpu) } } =20 + if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && + invtsc_mig_blocker =3D=3D NULL) { + error_setg(&invtsc_mig_blocker, + "State blocked by non-migratable CPU device (invtsc fla= g)"); + r =3D migrate_add_blocker(&invtsc_mig_blocker, &local_err); + if (r < 0) { + error_report_err(local_err); + return r; + } + } + + if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &hvf_state->hvf_caps->vmx_cap_pinbased)) { abort(); diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index 9380b90496..e56cd8411b 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -146,6 +146,10 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32= _t idx, CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XO= P | CPUID_EXT3_FMA4 | CPUID_EXT3_TBM; break; + case 0x80000007: + edx &=3D CPUID_APM_INVTSC; + eax =3D ebx =3D ecx =3D 0; + break; default: return 0; } --=20 2.36.1