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Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi") Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Song Gao --- hw/intc/loongarch_ipi.c | 347 --------------------------------------------= ---- 1 file changed, 347 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c deleted file mode 100644 index 44b3b9c138d6..000000000000 --- a/hw/intc/loongarch_ipi.c +++ /dev/null @@ -1,347 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * LoongArch ipi interrupt support - * - * Copyright (C) 2021 Loongson Technology Corporation Limited - */ - -#include "qemu/osdep.h" -#include "hw/boards.h" -#include "hw/sysbus.h" -#include "hw/intc/loongarch_ipi.h" -#include "hw/irq.h" -#include "hw/qdev-properties.h" -#include "qapi/error.h" -#include "qemu/log.h" -#include "exec/address-spaces.h" -#include "migration/vmstate.h" -#include "target/loongarch/cpu.h" -#include "trace.h" - -static MemTxResult loongarch_ipi_readl(void *opaque, hwaddr addr, - uint64_t *data, - unsigned size, MemTxAttrs attrs) -{ - IPICore *s; - LoongArchIPI *ipi =3D opaque; - uint64_t ret =3D 0; - int index =3D 0; - - s =3D &ipi->cpu[attrs.requester_id]; - addr &=3D 0xff; - switch (addr) { - case CORE_STATUS_OFF: - ret =3D s->status; - break; - case CORE_EN_OFF: - ret =3D s->en; - break; - case CORE_SET_OFF: - ret =3D 0; - break; - case CORE_CLEAR_OFF: - ret =3D 0; - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index =3D (addr - CORE_BUF_20) >> 2; - ret =3D s->buf[index]; - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); - break; - } - - trace_loongarch_ipi_read(size, (uint64_t)addr, ret); - *data =3D ret; - return MEMTX_OK; -} - -static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr add= r, - MemTxAttrs attrs) -{ - int i, mask =3D 0, data =3D 0; - - /* - * bit 27-30 is mask for byte writing, - * if the mask is 0, we need not to do anything. - */ - if ((val >> 27) & 0xf) { - data =3D address_space_ldl(env->address_space_iocsr, addr, - attrs, NULL); - for (i =3D 0; i < 4; i++) { - /* get mask for byte writing */ - if (val & (0x1 << (27 + i))) { - mask |=3D 0xff << (i * 8); - } - } - } - - data &=3D mask; - data |=3D (val >> 32) & ~mask; - address_space_stl(env->address_space_iocsr, addr, - data, attrs, NULL); -} - -static int archid_cmp(const void *a, const void *b) -{ - CPUArchId *archid_a =3D (CPUArchId *)a; - CPUArchId *archid_b =3D (CPUArchId *)b; - - return archid_a->arch_id - archid_b->arch_id; -} - -static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) -{ - CPUArchId apic_id, *found_cpu; - - apic_id.arch_id =3D id; - found_cpu =3D bsearch(&apic_id, ms->possible_cpus->cpus, - ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), - archid_cmp); - - return found_cpu; -} - -static CPUState *ipi_getcpu(int arch_id) -{ - MachineState *machine =3D MACHINE(qdev_get_machine()); - CPUArchId *archid; - - archid =3D find_cpu_by_archid(machine, arch_id); - if (archid) { - return CPU(archid->cpu); - } - - return NULL; -} - -static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) -{ - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid =3D extract32(val, 16, 10); - cs =3D ipi_getcpu(cpuid); - if (cs =3D=3D NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr =3D SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id =3D cs->cpu_index; - send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs); - return MEMTX_OK; -} - -static MemTxResult any_send(uint64_t val, MemTxAttrs attrs) -{ - uint32_t cpuid; - hwaddr addr; - CPUState *cs; - - cpuid =3D extract32(val, 16, 10); - cs =3D ipi_getcpu(cpuid); - if (cs =3D=3D NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - addr =3D val & 0xffff; - attrs.requester_id =3D cs->cpu_index; - send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs); - return MEMTX_OK; -} - -static MemTxResult loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_= t val, - unsigned size, MemTxAttrs attrs) -{ - LoongArchIPI *ipi =3D opaque; - IPICore *s; - int index =3D 0; - uint32_t cpuid; - uint8_t vector; - CPUState *cs; - - s =3D &ipi->cpu[attrs.requester_id]; - addr &=3D 0xff; - trace_loongarch_ipi_write(size, (uint64_t)addr, val); - switch (addr) { - case CORE_STATUS_OFF: - qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); - break; - case CORE_EN_OFF: - s->en =3D val; - break; - case CORE_SET_OFF: - s->status |=3D val; - if (s->status !=3D 0 && (s->status & s->en) !=3D 0) { - qemu_irq_raise(s->irq); - } - break; - case CORE_CLEAR_OFF: - s->status &=3D ~val; - if (s->status =3D=3D 0 && s->en !=3D 0) { - qemu_irq_lower(s->irq); - } - break; - case CORE_BUF_20 ... CORE_BUF_38 + 4: - index =3D (addr - CORE_BUF_20) >> 2; - s->buf[index] =3D val; - break; - case IOCSR_IPI_SEND: - cpuid =3D extract32(val, 16, 10); - /* IPI status vector */ - vector =3D extract8(val, 0, 5); - cs =3D ipi_getcpu(cpuid); - if (cs =3D=3D NULL) { - return MEMTX_DECODE_ERROR; - } - - /* override requester_id */ - attrs.requester_id =3D cs->cpu_index; - loongarch_ipi_writel(ipi, CORE_SET_OFF, BIT(vector), 4, attrs); - break; - default: - qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); - break; - } - - return MEMTX_OK; -} - -static const MemoryRegionOps loongarch_ipi_ops =3D { - .read_with_attrs =3D loongarch_ipi_readl, - .write_with_attrs =3D loongarch_ipi_writel, - .impl.min_access_size =3D 4, - .impl.max_access_size =3D 4, - .valid.min_access_size =3D 4, - .valid.max_access_size =3D 8, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -/* mail send and any send only support writeq */ -static MemTxResult loongarch_ipi_writeq(void *opaque, hwaddr addr, uint64_= t val, - unsigned size, MemTxAttrs attrs) -{ - MemTxResult ret =3D MEMTX_OK; - - addr &=3D 0xfff; - switch (addr) { - case MAIL_SEND_OFFSET: - ret =3D mail_send(val, attrs); - break; - case ANY_SEND_OFFSET: - ret =3D any_send(val, attrs); - break; - default: - break; - } - - return ret; -} - -static const MemoryRegionOps loongarch_ipi64_ops =3D { - .write_with_attrs =3D loongarch_ipi_writeq, - .impl.min_access_size =3D 8, - .impl.max_access_size =3D 8, - .valid.min_access_size =3D 8, - .valid.max_access_size =3D 8, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static void loongarch_ipi_realize(DeviceState *dev, Error **errp) -{ - LoongArchIPI *s =3D LOONGARCH_IPI(dev); - SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - int i; - - if (s->num_cpu =3D=3D 0) { - error_setg(errp, "num-cpu must be at least 1"); - return; - } - - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongarch_ipi_o= ps, - s, "loongarch_ipi_iocsr", 0x48); - - /* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */ - s->ipi_iocsr_mem.disable_reentrancy_guard =3D true; - - sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); - - memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), - &loongarch_ipi64_ops, - s, "loongarch_ipi64_iocsr", 0x118); - sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); - - s->cpu =3D g_new0(IPICore, s->num_cpu); - if (s->cpu =3D=3D NULL) { - error_setg(errp, "Memory allocation for ExtIOICore faile"); - return; - } - - for (i =3D 0; i < s->num_cpu; i++) { - qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); - } -} - -static const VMStateDescription vmstate_ipi_core =3D { - .name =3D "ipi-single", - .version_id =3D 2, - .minimum_version_id =3D 2, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(status, IPICore), - VMSTATE_UINT32(en, IPICore), - VMSTATE_UINT32(set, IPICore), - VMSTATE_UINT32(clear, IPICore), - VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_loongarch_ipi =3D { - .name =3D TYPE_LOONGARCH_IPI, - .version_id =3D 2, - .minimum_version_id =3D 2, - .fields =3D (const VMStateField[]) { - VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchIPI, num_cpu, - vmstate_ipi_core, IPICore), - VMSTATE_END_OF_LIST() - } -}; - -static Property ipi_properties[] =3D { - DEFINE_PROP_UINT32("num-cpu", LoongArchIPI, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), -}; - -static void loongarch_ipi_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->realize =3D loongarch_ipi_realize; - device_class_set_props(dc, ipi_properties); - dc->vmsd =3D &vmstate_loongarch_ipi; -} - -static void loongarch_ipi_finalize(Object *obj) -{ - LoongArchIPI *s =3D LOONGARCH_IPI(obj); - - g_free(s->cpu); -} - -static const TypeInfo loongarch_ipi_info =3D { - .name =3D TYPE_LOONGARCH_IPI, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(LoongArchIPI), - .class_init =3D loongarch_ipi_class_init, - .instance_finalize =3D loongarch_ipi_finalize, -}; - -static void loongarch_ipi_register_types(void) -{ - type_register_static(&loongarch_ipi_info); -} - -type_init(loongarch_ipi_register_types) --=20 2.43.0 From nobody Mon Nov 25 02:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240605-loongson3-ipi-v3-2-ddd2c0e03fa3@flygoat.com> References: <20240605-loongson3-ipi-v3-0-ddd2c0e03fa3@flygoat.com> In-Reply-To: <20240605-loongson3-ipi-v3-0-ddd2c0e03fa3@flygoat.com> To: qemu-devel@nongnu.org Cc: Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6577; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=LZOgZg61JSx7cogFY2kbLtUvCEt/U75uCJMoXwV6gt0=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrT4U3rmEpferWeZebnRa0nJooVTXnqcn+674Wu+X1xlS opiWCZDRykLgxgXg6yYIkuIgFLfhsaLC64/yPoDM4eVCWQIAxenAExkAQ/DP63UKfvvHp6/ls9/ 43bBh1pfDEuWN3Byyx+yLiltqTxg+YuRYdIMY8mLd7fyTNrzr+nFRBn71V98inz5+TPO6d+SWLW xjBcA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.168.172.159; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh8-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @flygoat.com) X-ZM-MESSAGEID: 1717553806965100007 The real IPI hardware have dedicated MMIO registers mapped into memory address space for every core. This is not used by LoongArch guest software but it is essential for CPU without IOCSR such as Loongson-3A1000. Implement it with existing infrastructure. Acked-by: Song Gao Signed-off-by: Jiaxun Yang --- hw/intc/loongson_ipi.c | 81 ++++++++++++++++++++++++++++++++------= ---- include/hw/intc/loongson_ipi.h | 2 ++ 2 files changed, 64 insertions(+), 19 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 93cc50a37a11..c8a25b4eb8e2 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -23,16 +23,14 @@ #endif #include "trace.h" =20 -static MemTxResult loongson_ipi_readl(void *opaque, hwaddr addr, +static MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { - IPICore *s; - LoongsonIPI *ipi =3D opaque; + IPICore *s =3D opaque; uint64_t ret =3D 0; int index =3D 0; =20 - s =3D &ipi->cpu[attrs.requester_id]; addr &=3D 0xff; switch (addr) { case CORE_STATUS_OFF: @@ -61,6 +59,21 @@ static MemTxResult loongson_ipi_readl(void *opaque, hwad= dr addr, return MEMTX_OK; } =20 +static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, + uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + LoongsonIPI *ipi =3D opaque; + IPICore *s; + + if (attrs.requester_id >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s =3D &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_readl(s, addr, data, size, attrs); +} + static AddressSpace *get_cpu_iocsr_as(CPUState *cpu) { #ifdef TARGET_LOONGARCH64 @@ -174,17 +187,17 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs = attrs) return send_ipi_data(cs, val, addr, attrs); } =20 -static MemTxResult loongson_ipi_writel(void *opaque, hwaddr addr, uint64_t= val, - unsigned size, MemTxAttrs attrs) +static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { - LoongsonIPI *ipi =3D opaque; - IPICore *s; + IPICore *s =3D opaque; + LoongsonIPI *ipi =3D s->ipi; int index =3D 0; uint32_t cpuid; uint8_t vector; CPUState *cs; =20 - s =3D &ipi->cpu[attrs.requester_id]; addr &=3D 0xff; trace_loongson_ipi_write(size, (uint64_t)addr, val); switch (addr) { @@ -215,13 +228,11 @@ static MemTxResult loongson_ipi_writel(void *opaque, = hwaddr addr, uint64_t val, /* IPI status vector */ vector =3D extract8(val, 0, 5); cs =3D ipi_getcpu(cpuid); - if (cs =3D=3D NULL) { + if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { return MEMTX_DECODE_ERROR; } - - /* override requester_id */ - attrs.requester_id =3D cs->cpu_index; - loongson_ipi_writel(ipi, CORE_SET_OFF, BIT(vector), 4, attrs); + loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + BIT(vector), 4, attrs); break; default: qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); @@ -231,9 +242,34 @@ static MemTxResult loongson_ipi_writel(void *opaque, h= waddr addr, uint64_t val, return MEMTX_OK; } =20 -static const MemoryRegionOps loongson_ipi_ops =3D { - .read_with_attrs =3D loongson_ipi_readl, - .write_with_attrs =3D loongson_ipi_writel, +static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) +{ + LoongsonIPI *ipi =3D opaque; + IPICore *s; + + if (attrs.requester_id >=3D ipi->num_cpu) { + return MEMTX_DECODE_ERROR; + } + + s =3D &ipi->cpu[attrs.requester_id]; + return loongson_ipi_core_writel(s, addr, val, size, attrs); +} + +static const MemoryRegionOps loongson_ipi_core_ops =3D { + .read_with_attrs =3D loongson_ipi_core_readl, + .write_with_attrs =3D loongson_ipi_core_writel, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps loongson_ipi_iocsr_ops =3D { + .read_with_attrs =3D loongson_ipi_iocsr_readl, + .write_with_attrs =3D loongson_ipi_iocsr_writel, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, .valid.min_access_size =3D 4, @@ -282,7 +318,7 @@ static void loongson_ipi_realize(DeviceState *dev, Erro= r **errp) return; } =20 - memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongson_ipi_op= s, + memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongson_ipi_io= csr_ops, s, "loongson_ipi_iocsr", 0x48); =20 /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ @@ -297,11 +333,18 @@ static void loongson_ipi_realize(DeviceState *dev, Er= ror **errp) =20 s->cpu =3D g_new0(IPICore, s->num_cpu); if (s->cpu =3D=3D NULL) { - error_setg(errp, "Memory allocation for ExtIOICore faile"); + error_setg(errp, "Memory allocation for IPICore faile"); return; } =20 for (i =3D 0; i < s->num_cpu; i++) { + s->cpu[i].ipi =3D s; + s->cpu[i].ipi_mmio_mem =3D g_new0(MemoryRegion, 1); + g_autofree char *name =3D g_strdup_printf("loongson_ipi_cpu%d_mmio= ", i); + memory_region_init_io(s->cpu[i].ipi_mmio_mem, OBJECT(dev), + &loongson_ipi_core_ops, &s->cpu[i], name, 0x= 48); + sysbus_init_mmio(sbd, s->cpu[i].ipi_mmio_mem); + qdev_init_gpio_out(dev, &s->cpu[i].irq, 1); } } diff --git a/include/hw/intc/loongson_ipi.h b/include/hw/intc/loongson_ipi.h index 2c0e8820f5ec..3f795edbf3cd 100644 --- a/include/hw/intc/loongson_ipi.h +++ b/include/hw/intc/loongson_ipi.h @@ -34,6 +34,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongsonIPI, LOONGSON_IPI) =20 typedef struct IPICore { + LoongsonIPI *ipi; + MemoryRegion *ipi_mmio_mem; uint32_t status; uint32_t en; uint32_t set; --=20 2.43.0 From nobody Mon Nov 25 02:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240605-loongson3-ipi-v3-3-ddd2c0e03fa3@flygoat.com> References: <20240605-loongson3-ipi-v3-0-ddd2c0e03fa3@flygoat.com> In-Reply-To: <20240605-loongson3-ipi-v3-0-ddd2c0e03fa3@flygoat.com> To: qemu-devel@nongnu.org Cc: Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5931; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=PU0pRzZdrbatFFMu+BeAzyWRMViyfj/mEDg8DqP63O4=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrT4U3pTWL36XyR679h72b9Vb5Z1XMSh2wJf5do6Tnew7 6xhVFjZUcrCIMbFICumyBIioNS3ofHigusPsv7AzGFlAhnCwMUpABNJvcHIMDNBqXma1JOfVgxc PqonxOdH8C+r4710/5HgPY7j/Ga5GYwM21fb+vx7nFG+5SbnC402FoWCuvPycUGH83/Fl2kaHWD lAgA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.168.172.159; envelope-from=jiaxun.yang@flygoat.com; helo=fhigh8-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @flygoat.com) X-ZM-MESSAGEID: 1717553817141100003 Wire up loongson_ipi device for loongson3_virt machine, so we can have SMP support for TCG backend as well. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/Kconfig | 1 + hw/mips/loongson3_bootp.c | 2 -- hw/mips/loongson3_bootp.h | 3 +++ hw/mips/loongson3_virt.c | 39 +++++++++++++++++++++++++++++++++++++-- 4 files changed, 41 insertions(+), 4 deletions(-) diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index a7f26edebe84..692bede538ee 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -67,6 +67,7 @@ config LOONGSON3V imply USB_OHCI_PCI select SERIAL select GOLDFISH_RTC + select LOONGSON_IPI select LOONGSON_LIOINTC select PCI_EXPRESS_GENERIC_BRIDGE select MSI_NONBROKEN diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c index 03a10b63c1b4..b97b81903b74 100644 --- a/hw/mips/loongson3_bootp.c +++ b/hw/mips/loongson3_bootp.c @@ -25,8 +25,6 @@ #include "hw/boards.h" #include "hw/mips/loongson3_bootp.h" =20 -#define LOONGSON3_CORE_PER_NODE 4 - static void init_cpu_info(void *g_cpuinfo, uint64_t cpu_freq) { struct efi_cpuinfo_loongson *c =3D g_cpuinfo; diff --git a/hw/mips/loongson3_bootp.h b/hw/mips/loongson3_bootp.h index 1b0dd3b59171..9091265df7fc 100644 --- a/hw/mips/loongson3_bootp.h +++ b/hw/mips/loongson3_bootp.h @@ -200,6 +200,8 @@ struct boot_params { struct efi_reset_system_t reset_system; }; =20 +#define LOONGSON3_CORE_PER_NODE 4 + /* Overall MMIO & Memory layout */ enum { VIRT_LOWMEM, @@ -211,6 +213,7 @@ enum { VIRT_BIOS_ROM, VIRT_UART, VIRT_LIOINTC, + VIRT_IPI, VIRT_PCIE_MMIO, VIRT_HIGHMEM }; diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index 440268a07430..3a4105228c1d 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -36,6 +36,7 @@ #include "hw/mips/loongson3_bootp.h" #include "hw/misc/unimp.h" #include "hw/intc/i8259.h" +#include "hw/intc/loongson_ipi.h" #include "hw/loader.h" #include "hw/isa/superio.h" #include "hw/pci/msi.h" @@ -74,6 +75,7 @@ const MemMapEntry virt_memmap[] =3D { [VIRT_PCIE_ECAM] =3D { 0x1a000000, 0x2000000 }, [VIRT_BIOS_ROM] =3D { 0x1fc00000, 0x200000 }, [VIRT_UART] =3D { 0x1fe001e0, 0x8 }, + [VIRT_IPI] =3D { 0x3ff01000, 0x400 }, [VIRT_LIOINTC] =3D { 0x3ff01400, 0x64 }, [VIRT_PCIE_MMIO] =3D { 0x40000000, 0x40000000 }, [VIRT_HIGHMEM] =3D { 0x80000000, 0x0 }, /* Variable */ @@ -485,6 +487,7 @@ static void mips_loongson3_virt_init(MachineState *mach= ine) Clock *cpuclk; CPUMIPSState *env; DeviceState *liointc; + DeviceState *ipi =3D NULL; char *filename; const char *kernel_cmdline =3D machine->kernel_cmdline; const char *kernel_filename =3D machine->kernel_filename; @@ -494,6 +497,7 @@ static void mips_loongson3_virt_init(MachineState *mach= ine) MemoryRegion *ram =3D g_new(MemoryRegion, 1); MemoryRegion *bios =3D g_new(MemoryRegion, 1); MemoryRegion *iomem =3D g_new(MemoryRegion, 1); + MemoryRegion *iocsr =3D g_new(MemoryRegion, 1); =20 /* TODO: TCG will support all CPU types */ if (!kvm_enabled()) { @@ -527,6 +531,19 @@ static void mips_loongson3_virt_init(MachineState *mac= hine) create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB); create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB); =20 + memory_region_init(iocsr, OBJECT(machine), "loongson3.iocsr", UINT32_M= AX); + + /* IPI controller is in kernel for KVM */ + if (!kvm_enabled()) { + ipi =3D qdev_new(TYPE_LOONGSON_IPI); + qdev_prop_set_uint32(ipi, "num-cpu", machine->smp.cpus); + sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); + memory_region_add_subregion(iocsr, SMP_IPI_MAILBOX, + sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); + memory_region_add_subregion(iocsr, MAIL_SEND_ADDR, + sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); + } + liointc =3D qdev_new("loongson.liointc"); sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal); =20 @@ -543,6 +560,8 @@ static void mips_loongson3_virt_init(MachineState *mach= ine) clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ); =20 for (i =3D 0; i < machine->smp.cpus; i++) { + int node =3D i / LOONGSON3_CORE_PER_NODE; + int core =3D i % LOONGSON3_CORE_PER_NODE; int ip; =20 /* init CPUs */ @@ -553,12 +572,28 @@ static void mips_loongson3_virt_init(MachineState *ma= chine) cpu_mips_clock_init(cpu); qemu_register_reset(main_cpu_reset, cpu); =20 - if (i >=3D 4) { + if (ipi) { + hwaddr base =3D ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].b= ase; + base +=3D core * 0x100; + qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]); + sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base); + } + + if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { + MemoryRegion *core_iocsr =3D g_new(MemoryRegion, 1); + g_autofree char *name =3D g_strdup_printf("loongson3.core%d_io= csr", i); + memory_region_init_alias(core_iocsr, OBJECT(cpu), name, + iocsr, 0, UINT32_MAX); + memory_region_add_subregion(&MIPS_CPU(cpu)->env.iocsr.mr, + 0, core_iocsr); + } + + if (node > 0) { continue; /* Only node-0 can be connected to LIOINTC */ } =20 for (ip =3D 0; ip < 4 ; ip++) { - int pin =3D i * 4 + ip; + int pin =3D core * LOONGSON3_CORE_PER_NODE + ip; sysbus_connect_irq(SYS_BUS_DEVICE(liointc), pin, cpu->env.irq[ip + 2]); } --=20 2.43.0 From nobody Mon Nov 25 02:36:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=flygoat.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=103.168.172.144; envelope-from=jiaxun.yang@flygoat.com; helo=fout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @flygoat.com) X-ZM-MESSAGEID: 1717553823107100011 cpu_by_arch_id is doing the same thing as our ipi_getcpu logic. Signed-off-by: Jiaxun Yang Reviewed-by: Song Gao --- hw/intc/loongson_ipi.c | 39 +++------------------------------------ 1 file changed, 3 insertions(+), 36 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index c8a25b4eb8e2..b3cda5972793 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -118,39 +118,6 @@ static MemTxResult send_ipi_data(CPUState *cpu, uint64= _t val, hwaddr addr, return MEMTX_OK; } =20 -static int archid_cmp(const void *a, const void *b) -{ - CPUArchId *archid_a =3D (CPUArchId *)a; - CPUArchId *archid_b =3D (CPUArchId *)b; - - return archid_a->arch_id - archid_b->arch_id; -} - -static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) -{ - CPUArchId apic_id, *found_cpu; - - apic_id.arch_id =3D id; - found_cpu =3D bsearch(&apic_id, ms->possible_cpus->cpus, - ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), - archid_cmp); - - return found_cpu; -} - -static CPUState *ipi_getcpu(int arch_id) -{ - MachineState *machine =3D MACHINE(qdev_get_machine()); - CPUArchId *archid; - - archid =3D find_cpu_by_archid(machine, arch_id); - if (archid) { - return CPU(archid->cpu); - } - - return NULL; -} - static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs) { uint32_t cpuid; @@ -158,7 +125,7 @@ static MemTxResult mail_send(uint64_t val, MemTxAttrs a= ttrs) CPUState *cs; =20 cpuid =3D extract32(val, 16, 10); - cs =3D ipi_getcpu(cpuid); + cs =3D cpu_by_arch_id(cpuid); if (cs =3D=3D NULL) { return MEMTX_DECODE_ERROR; } @@ -176,7 +143,7 @@ static MemTxResult any_send(uint64_t val, MemTxAttrs at= trs) CPUState *cs; =20 cpuid =3D extract32(val, 16, 10); - cs =3D ipi_getcpu(cpuid); + cs =3D cpu_by_arch_id(cpuid); if (cs =3D=3D NULL) { return MEMTX_DECODE_ERROR; } @@ -227,7 +194,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaqu= e, hwaddr addr, cpuid =3D extract32(val, 16, 10); /* IPI status vector */ vector =3D extract8(val, 0, 5); - cs =3D ipi_getcpu(cpuid); + cs =3D cpu_by_arch_id(cpuid); if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { return MEMTX_DECODE_ERROR; } --=20 2.43.0