From nobody Mon Nov 25 04:49:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1717492529; cv=none; d=zohomail.com; s=zohoarc; b=DqXZJOzY65GullR13bmA7I1qRn75JJzKvmT3+3VZTUVLp/eHSiKpj7UEicYatKf7p0krl3W4WzCxRi5FIDeKAcwGuHhCj9ruzFf1Jh3V8Cbcvl2RYCD5uQCjBhuA0/JPau30apFDebppUHmRM+gzpfdpwzD0dZ/+hZ9S72R5eLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717492529; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=aT30bYFME7OAIaQjley+YTko2xGZ6YuLvLOYV2kRbgY=; b=JoBTz2wgFpS00JFl8KUJl0F0uZioxtc811FlDKN0+Ot4VCGQ+OtxuVS9kybRwpZ91jwk+bX4aAmnly62QRy05Dxv/GB8GSNrVkXZzcHbJG39ZrqPKpCsqyVxM0uOa9TRQP3ypjZ6dJrqe0onYZVeiK2eD7ikTIONlclsAECgEh4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1717492529669359.7962263585666; Tue, 4 Jun 2024 02:15:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sEQG5-0006bo-S8; Tue, 04 Jun 2024 05:15:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEQFw-0006ag-Q4; Tue, 04 Jun 2024 05:15:01 -0400 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEQFt-0003QL-ED; Tue, 04 Jun 2024 05:15:00 -0400 Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 45494wWf090663; Tue, 4 Jun 2024 17:04:58 +0800 (+08) (envelope-from yumin686@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 45494epg090481; Tue, 4 Jun 2024 17:04:40 +0800 (+08) (envelope-from yumin686@andestech.com) Received: from lubuntu-vb.andestech.com (10.0.12.32) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Tue, 4 Jun 2024 17:04:40 +0800 To: , CC: , , , , , , , Alvin Chang Subject: [PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR Date: Tue, 4 Jun 2024 17:04:34 +0800 Message-ID: <20240604090434.37136-1-yumin686@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.12.32] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 45494wWf090663 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=yumin686@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Yu-Ming Chang From: Yu-Ming Chang via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1717492530865100003 Content-Type: text/plain; charset="utf-8" Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a regis= ter holding a zero value other than x0, the instruction will still attempt to w= rite the unmodified value back to the CSR and will cause any attendant side effe= cts. So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies a register holding a zero value, an illegal instruction exception should be raised. Signed-off-by: Yu-Ming Chang Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis --- Hi Alistair, This fixed the issue of riscv_csrrw_debug(). Best regards, Yuming target/riscv/cpu.h | 4 +++ target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++---- target/riscv/op_helper.c | 6 ++--- 3 files changed, 58 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2d0c02c35b..72921bafc0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -708,6 +708,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, void riscv_cpu_update_mask(CPURISCVState *env); bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 +RISCVException riscv_csrr(CPURISCVState *env, int csrno, + target_ulong *ret_value); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); @@ -740,6 +742,8 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState= *env, int csrno, target_ulong new_value, target_ulong write_mask); =20 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, + Int128 *ret_value); RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, Int128 *ret_value, Int128 new_value, Int128 write_mask); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 726096444f..aa765678b9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -4312,7 +4312,7 @@ static RISCVException rmw_seed(CPURISCVState *env, in= t csrno, =20 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, int csrno, - bool write_mask) + bool write) { /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails = */ bool read_only =3D get_field(csrno, 0xC00) =3D=3D 3; @@ -4334,7 +4334,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, } =20 /* read / write check */ - if (write_mask && read_only) { + if (write && read_only) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -4421,11 +4421,22 @@ static RISCVException riscv_csrrw_do64(CPURISCVStat= e *env, int csrno, return RISCV_EXCP_NONE; } =20 +RISCVException riscv_csrr(CPURISCVState *env, int csrno, + target_ulong *ret_value) +{ + RISCVException ret =3D riscv_csrrw_check(env, csrno, false); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + return riscv_csrrw_do64(env, csrno, ret_value, 0, 0); +} + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVException ret =3D riscv_csrrw_check(env, csrno, write_mask); + RISCVException ret =3D riscv_csrrw_check(env, csrno, true); if (ret !=3D RISCV_EXCP_NONE) { return ret; } @@ -4473,13 +4484,45 @@ static RISCVException riscv_csrrw_do128(CPURISCVSta= te *env, int csrno, return RISCV_EXCP_NONE; } =20 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, + Int128 *ret_value) +{ + RISCVException ret; + + ret =3D riscv_csrrw_check(env, csrno, false); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + if (csr_ops[csrno].read128) { + return riscv_csrrw_do128(env, csrno, ret_value, + int128_zero(), int128_zero()); + } + + /* + * Fall back to 64-bit version for now, if the 128-bit alternative isn= 't + * at all defined. + * Note, some CSRs don't need to extend to MXLEN (64 upper bits non + * significant), for those, this fallback is correctly handling the + * accesses + */ + target_ulong old_value; + ret =3D riscv_csrrw_do64(env, csrno, &old_value, + (target_ulong)0, + (target_ulong)0); + if (ret =3D=3D RISCV_EXCP_NONE && ret_value) { + *ret_value =3D int128_make64(old_value); + } + return ret; +} + RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, Int128 *ret_value, Int128 new_value, Int128 write_mask) { RISCVException ret; =20 - ret =3D riscv_csrrw_check(env, csrno, int128_nz(write_mask)); + ret =3D riscv_csrrw_check(env, csrno, true); if (ret !=3D RISCV_EXCP_NONE) { return ret; } @@ -4518,7 +4561,11 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env,= int csrno, #if !defined(CONFIG_USER_ONLY) env->debugger =3D true; #endif - ret =3D riscv_csrrw(env, csrno, ret_value, new_value, write_mask); + if (!write_mask) { + ret =3D riscv_csrr(env, csrno, ret_value); + } else { + ret =3D riscv_csrrw(env, csrno, ret_value, new_value, write_mask); + } #if !defined(CONFIG_USER_ONLY) env->debugger =3D false; #endif diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f414aaebdb..b95d47e9ac 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -51,7 +51,7 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) } =20 target_ulong val =3D 0; - RISCVException ret =3D riscv_csrrw(env, csr, &val, 0, 0); + RISCVException ret =3D riscv_csrr(env, csr, &val); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); @@ -84,9 +84,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, target_ulong helper_csrr_i128(CPURISCVState *env, int csr) { Int128 rv =3D int128_zero(); - RISCVException ret =3D riscv_csrrw_i128(env, csr, &rv, - int128_zero(), - int128_zero()); + RISCVException ret =3D riscv_csrr_i128(env, csr, &rv); =20 if (ret !=3D RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); --=20 2.34.1