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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1dcb56014sm7115617a91.25.2024.06.03.23.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 23:22:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717482173; x=1718086973; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1mVeGIiMOTpViZqT/i0mT5bp2ZCtBNFV+Qcrg20yga8=; b=QivG5cvmXuJL9p4pIeiZXPYRQruydaVEWU+IfRDBHGX9RLCzJTvb0SKYrm6lYB5ljJ qNAWrYS8kVaE3Vktw24JqXmDkx+WKMjmn30cknXko/rCBAfhW8yLHSWKl1xf2VYsj4bV UYiOcuveQw8eNrQlkPr4a+8B50wBEptwxB4i8ATs3oSOX/VGExfewYQo41Bs5NCQU9ST n5nZB/5yLMc41Jt9kO1GlmvsobBs6lClbUIBkRtUNz7N90zpgve71g4gWu5i4hoWZz04 rxjjba75b8Pl9Hm0EsBQql2kaFAJUERCxLF8OYjBDgSvJyaQwSwNfuXt1C1sV95JSAeN 056Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717482173; x=1718086973; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1mVeGIiMOTpViZqT/i0mT5bp2ZCtBNFV+Qcrg20yga8=; b=Qhm6OdGRyQ6oOGA2kNAci2Py8fvBZvcVN5ATAvtjmnoL9LYMHiwqLIROVxxXzChyxS w9ziBPq+WBKlxq0dESJ/rgses6/+/s3mRlcd3lYSbE22codz6A95LaFqVcKmzjjHqHPl WyvLCCTEBCl3lZLl3z5Z0BWun+pVKoPFiTNgElhFPaaqhSszWTzJxeJDa25jNVclWQgz X1vDGN9M795VfjUx5PQ3Z/qvo5bmFgY44YA1X4WiJ8UMxtw6as+ijkMm6dlP/gaxnoMj HKjHUb04IWyyoqsUwkHcz4svp6jtnpeJCjMBfYeb8FfL7ZKM6gx0yI8hzwG8CZqMo4YE t/9Q== X-Gm-Message-State: AOJu0YylQKgAKC/2GgoH1Gp0XGGXwnZ65uxnrVRbhrATvBGR8Klbs5ph 0dKfDq5MSAxS7oziXRapYfJAtx23GSTOX5VPojDa5ptoeQJtoCvYpKE5Gku2TOWDefknWqZ0N1y jhX/WS6pB/TKPSZrbzYnUXmvkX1UUHXai0V23XBGXgDfRoPBsSbDSwRLClrbr/bFKujYLw+HAy3 Ed1hZe80aBP7sCK3TDmAtyEFiurCjo9HVipr4= X-Google-Smtp-Source: AGHT+IHmJQVRTWRwonwVjH66PT6OM0HAUviYRMBDy8jVXUmYQ1zD5KaUFC+XA1WSKYV5PFsPr/ZMqg== X-Received: by 2002:a17:90b:245:b0:2c1:c648:14d2 with SMTP id 98e67ed59e1d1-2c1dc55ff68mr10378867a91.1.1717482172624; Mon, 03 Jun 2024 23:22:52 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang Subject: [PATCH v3 6/6] target/riscv: Reserve exception codes for sw-check and hw-err Date: Tue, 4 Jun 2024 14:27:47 +0800 Message-Id: <20240604062747.9212-7-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604062747.9212-1-fea.wang@sifive.com> References: <20240604062747.9212-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=fea.wang@sifive.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1717482245574100001 Content-Type: text/plain; charset="utf-8" Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f888025c59..f037f727d9 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -673,6 +673,8 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_SW_CHECK =3D 0x12, /* since: priv-1.13.0 */ + RISCV_EXCP_HW_ERR =3D 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT =3D 0x15, RISCV_EXCP_VIRT_INSTRUCTION_FAULT =3D 0x16, --=20 2.34.1