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Wang" , Frank Chang Subject: [PATCH v3 1/6] target/riscv: Reuse the conversion function of priv_spec Date: Tue, 4 Jun 2024 14:27:42 +0800 Message-Id: <20240604062747.9212-2-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604062747.9212-1-fea.wang@sifive.com> References: <20240604062747.9212-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=fea.wang@sifive.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1717482237497100010 Content-Type: text/plain; charset="utf-8" From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 13 ++++--------- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cee6fc4a9a..e9e69b9863 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1786,7 +1786,7 @@ static int priv_spec_from_str(const char *priv_spec_s= tr) return priv_version; } =20 -static const char *priv_spec_to_str(int priv_version) +const char *priv_spec_to_str(int priv_version) { switch (priv_version) { case PRIV_VERSION_1_10_0: diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 12d8b5344a..94600b91fa 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -829,4 +829,5 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32= _bit); /* Implemented in th_csr.c */ void th_register_custom_csrs(RISCVCPU *cpu); =20 +const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 683f604d9f..60fe0fd060 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -76,16 +76,11 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uin= t32_t bit, =20 static const char *cpu_priv_ver_to_str(int priv_ver) { - switch (priv_ver) { - case PRIV_VERSION_1_10_0: - return "v1.10.0"; - case PRIV_VERSION_1_11_0: - return "v1.11.0"; - case PRIV_VERSION_1_12_0: - return "v1.12.0"; - } + const char *priv_spec_str =3D priv_spec_to_str(priv_ver); =20 - g_assert_not_reached(); + g_assert(priv_spec_str); + + return priv_spec_str; } =20 static void riscv_cpu_synchronize_from_tb(CPUState *cs, --=20 2.34.1