From nobody Mon Nov 25 07:39:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1717480056; cv=none; d=zohomail.com; s=zohoarc; b=bklSuusbCFPytp3ni0fX2Br/nrXwmjFiz6jedQ6mvGAGWT9EE01O6vOU8xlN3QRGHqyr8l5u1c98huhR/aOlTiVA+ZU3W4DFSioPoOxrVeezhBRGm4wjzenOYJJD2rHsmOo38YK8AHixH5SxbsgbXNDkhEVk0svH2ClMiB2BAv8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717480056; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=KpBT36/Sf+V7oaZspXR05aOFNOw/DZvRpxWjKobb4+o=; b=doMNbOmcn7qcd7eEBV7/349eqe9Gf9pzrr6ecNFjOKtXe1jKw/X1NRD7biM66Ooh0D9BqecJTJ6eVP1KoHJ8vj/2ALA0VTxE8RiZdJjaKndjao/WitLw/WUR0MdmCgfOGUM/Vef8TGIcPXS3AS/SZITbJQjXb5CW/WlRYcavz9s= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 171748005654788.07234754558874; Mon, 3 Jun 2024 22:47:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sEMyt-0005ds-Um; Tue, 04 Jun 2024 01:45:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEMys-0005de-TX; Tue, 04 Jun 2024 01:45:10 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEMyr-0008TH-0f; Tue, 04 Jun 2024 01:45:10 -0400 Received: from TWMBX02.aspeed.com (192.168.0.24) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Tue, 4 Jun 2024 13:44:43 +0800 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX02.aspeed.com (192.168.0.25) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jun 2024 13:44:43 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 4 Jun 2024 13:44:42 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , Alistair Francis , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v5 07/17] aspeed/smc: support dma start length and 1 byte length unit Date: Tue, 4 Jun 2024 13:44:28 +0800 Message-ID: <20240604054438.3424349-8-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240604054438.3424349-1-jamin_lin@aspeedtech.com> References: <20240604054438.3424349-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Fail (TWMBX02.aspeed.com: domain of jamin_lin@aspeedtech.com does not designate 192.168.10.10 as permitted sender) receiver=TWMBX02.aspeed.com; client-ip=192.168.10.10; helo=localhost.localdomain; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1717480057854100003 DMA length is from 1 byte to 32MB for AST2600 and AST10x0 and DMA length is from 4 bytes to 32MB for AST2500. In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte data for AST2600 and AST10x0 and 4 bytes data for AST2500. To support all ASPEED SOCs, adds dma_start_length parameter to store the start length, add helper routines function to compute the dma length and update DMA_LENGTH mask to "1FFFFFF" to support dma 1 byte length unit for AST2600 and AST1030. Currently, only supports dma length 4 bytes aligned. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 43 ++++++++++++++++++++++++++++++------- include/hw/ssi/aspeed_smc.h | 1 + 2 files changed, 36 insertions(+), 8 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index fe1cd96b80..0b8488a113 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -178,13 +178,17 @@ * DMA flash addresses should be 4 bytes aligned and the valid address * range is 0x20000000 - 0x2FFFFFFF. * - * DMA length is from 4 bytes to 32MB + * DMA length is from 4 bytes to 32MB (AST2500) * 0: 4 bytes - * 0x7FFFFF: 32M bytes + * 0x1FFFFFC: 32M bytes + * + * DMA length is from 1 byte to 32MB (AST2600, AST10x0) + * 0: 1 byte + * 0x1FFFFFF: 32M bytes */ #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask) #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask) -#define DMA_LENGTH(val) ((val) & 0x01FFFFFC) +#define DMA_LENGTH(val) ((val) & 0x01FFFFFF) =20 /* Flash opcodes. */ #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ @@ -843,6 +847,13 @@ static bool aspeed_smc_inject_read_failure(AspeedSMCSt= ate *s) } } =20 +static uint32_t aspeed_smc_dma_len(AspeedSMCState *s) +{ + AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(s); + + return QEMU_ALIGN_UP(s->regs[R_DMA_LEN] + asc->dma_start_length, 4); +} + /* * Accumulate the result of the reads to provide a checksum that will * be used to validate the read timing settings. @@ -850,6 +861,7 @@ static bool aspeed_smc_inject_read_failure(AspeedSMCSta= te *s) static void aspeed_smc_dma_checksum(AspeedSMCState *s) { MemTxResult result; + uint32_t dma_len; uint32_t data; =20 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { @@ -861,7 +873,9 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) aspeed_smc_dma_calibration(s); } =20 - while (s->regs[R_DMA_LEN]) { + dma_len =3D aspeed_smc_dma_len(s); + + while (dma_len) { data =3D address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_AD= DR], MEMTXATTRS_UNSPECIFIED, &result); if (result !=3D MEMTX_OK) { @@ -877,7 +891,8 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) */ s->regs[R_DMA_CHECKSUM] +=3D data; s->regs[R_DMA_FLASH_ADDR] +=3D 4; - s->regs[R_DMA_LEN] -=3D 4; + dma_len -=3D 4; + s->regs[R_DMA_LEN] =3D dma_len; } =20 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { @@ -889,14 +904,17 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) static void aspeed_smc_dma_rw(AspeedSMCState *s) { MemTxResult result; + uint32_t dma_len; uint32_t data; =20 + dma_len =3D aspeed_smc_dma_len(s); + trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? "write" : "read", s->regs[R_DMA_FLASH_ADDR], s->regs[R_DMA_DRAM_ADDR], - s->regs[R_DMA_LEN]); - while (s->regs[R_DMA_LEN]) { + dma_len); + while (dma_len) { if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { data =3D address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_= ADDR], MEMTXATTRS_UNSPECIFIED, &result); @@ -937,7 +955,8 @@ static void aspeed_smc_dma_rw(AspeedSMCState *s) */ s->regs[R_DMA_FLASH_ADDR] +=3D 4; s->regs[R_DMA_DRAM_ADDR] +=3D 4; - s->regs[R_DMA_LEN] -=3D 4; + dma_len -=3D 4; + s->regs[R_DMA_LEN] =3D dma_len; s->regs[R_DMA_CHECKSUM] +=3D data; } } @@ -1382,6 +1401,7 @@ static void aspeed_2400_fmc_class_init(ObjectClass *k= lass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x1FFFFFFC; + asc->dma_start_length =3D 4; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_smc_reg_to_segment; @@ -1465,6 +1485,7 @@ static void aspeed_2500_fmc_class_init(ObjectClass *k= lass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x3FFFFFFC; + asc->dma_start_length =3D 4; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_smc_reg_to_segment; @@ -1621,6 +1642,7 @@ static void aspeed_2600_fmc_class_init(ObjectClass *k= lass, void *data) ASPEED_SMC_FEATURE_WDT_CONTROL; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x3FFFFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; @@ -1659,6 +1681,7 @@ static void aspeed_2600_spi1_class_init(ObjectClass *= klass, void *data) ASPEED_SMC_FEATURE_DMA_GRANT; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x3FFFFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; @@ -1698,6 +1721,7 @@ static void aspeed_2600_spi2_class_init(ObjectClass *= klass, void *data) ASPEED_SMC_FEATURE_DMA_GRANT; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x3FFFFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; @@ -1779,6 +1803,7 @@ static void aspeed_1030_fmc_class_init(ObjectClass *k= lass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x000BFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_1030_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_1030_smc_reg_to_segment; @@ -1816,6 +1841,7 @@ static void aspeed_1030_spi1_class_init(ObjectClass *= klass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x000BFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; @@ -1852,6 +1878,7 @@ static void aspeed_1030_spi2_class_init(ObjectClass *= klass, void *data) asc->features =3D ASPEED_SMC_FEATURE_DMA; asc->dma_flash_mask =3D 0x0FFFFFFC; asc->dma_dram_mask =3D 0x000BFFFC; + asc->dma_start_length =3D 1; asc->nregs =3D ASPEED_SMC_R_MAX; asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 8791cc0ecb..d305ce2e2f 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -107,6 +107,7 @@ struct AspeedSMCClass { uint32_t features; hwaddr dma_flash_mask; hwaddr dma_dram_mask; + uint32_t dma_start_length; uint32_t nregs; uint32_t (*segment_to_reg)(const AspeedSMCState *s, const AspeedSegments *seg); --=20 2.25.1