From nobody Mon Nov 25 07:53:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1717480066; cv=none; d=zohomail.com; s=zohoarc; b=T/IIby/u59iGRoN9xsi9KfCF04N0qCTsuatIse8ziDE3ndLNabXu6ef1CAyT1TToTp/aGvKz1ZEPo5e7y9vCsVuKlWHHj/bh7Vy2Z6oCOrPhLqQl+TwUD2VwVztl18z0cN8x0LiXgsofevrDrErZnxSEJ/sJ1QPMZPyGdXmo8ek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717480066; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=l4dBP1Kk5CYHJ8vJiuk6fYDgTxlzFI+c6QAziPR5xus=; b=WL5BegYFUihqeA7VKm11do2X9+jfqDo8nYuNgaWrKLUDJjthM1056fHEr3KGgc17ImeXVx+GczgswL0Cob0MXcxEOGAvBF5BNETEDI8ESr5IQYKEwzFqgnsCpXfX/eAispOcivqqsg9vgwMsF5GQM8pQ5aGdOn5LoKL4mnnNjlo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17174800668660.08501167279666788; Mon, 3 Jun 2024 22:47:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sEMz2-0005tu-MQ; Tue, 04 Jun 2024 01:45:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEMz0-0005sQ-UU; Tue, 04 Jun 2024 01:45:18 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEMyy-0008TH-Uo; Tue, 04 Jun 2024 01:45:18 -0400 Received: from TWMBX02.aspeed.com (192.168.0.24) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Tue, 4 Jun 2024 13:44:44 +0800 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX02.aspeed.com (192.168.0.25) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Jun 2024 13:44:44 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 4 Jun 2024 13:44:44 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , Alistair Francis , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v5 10/17] aspeed/smc: Add AST2700 support Date: Tue, 4 Jun 2024 13:44:31 +0800 Message-ID: <20240604054438.3424349-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240604054438.3424349-1-jamin_lin@aspeedtech.com> References: <20240604054438.3424349-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Fail (TWMBX02.aspeed.com: domain of jamin_lin@aspeedtech.com does not designate 192.168.10.10 as permitted sender) receiver=TWMBX02.aspeed.com; client-ip=192.168.10.10; helo=localhost.localdomain; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1717480067892100001 Content-Type: text/plain; charset="utf-8" AST2700 fmc/spi controller's address decoding unit is 64KB and only bits [31:16] are used for decoding. Introduce seg_to_reg and reg_to_seg handlers for ast2700 fmc/spi controller. In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler. AST2700 is a 64 bits quad core CPUs(Cortex-a35). Introduce a new "aspeed_2700_smc_flash_ops" and set its valid "max_access_size" 8 for 64 bits data format access. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 234 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 233 insertions(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 129d06690d..49205ab76d 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -185,7 +185,7 @@ * 0: 4 bytes * 0x1FFFFFC: 32M bytes * - * DMA length is from 1 byte to 32MB (AST2600, AST10x0) + * DMA length is from 1 byte to 32MB (AST2600, AST10x0 and AST2700) * 0: 1 byte * 0x1FFFFFF: 32M bytes */ @@ -1938,6 +1938,234 @@ static const TypeInfo aspeed_1030_spi2_info =3D { .class_init =3D aspeed_1030_spi2_class_init, }; =20 +/* + * The FMC Segment Registers of the AST2700 have a 64KB unit. + * Only bits [31:16] are used for decoding. + */ +#define AST2700_SEG_ADDR_MASK 0xffff0000 + +static uint32_t aspeed_2700_smc_segment_to_reg(const AspeedSMCState *s, + const AspeedSegments *seg) +{ + uint32_t reg =3D 0; + + /* Disabled segments have a nil register */ + if (!seg->size) { + return 0; + } + + reg |=3D (seg->addr & AST2700_SEG_ADDR_MASK) >> 16; /* start offset */ + reg |=3D (seg->addr + seg->size - 1) & AST2700_SEG_ADDR_MASK; /* end o= ffset */ + return reg; +} + +static void aspeed_2700_smc_reg_to_segment(const AspeedSMCState *s, + uint32_t reg, AspeedSegments *s= eg) +{ + uint32_t start_offset =3D (reg << 16) & AST2700_SEG_ADDR_MASK; + uint32_t end_offset =3D reg & AST2700_SEG_ADDR_MASK; + AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(s); + + if (reg) { + seg->addr =3D asc->flash_window_base + start_offset; + seg->size =3D end_offset + (64 * KiB) - start_offset; + } else { + seg->addr =3D asc->flash_window_base; + seg->size =3D 0; + } +} + +static const uint32_t aspeed_2700_fmc_resets[ASPEED_SMC_R_MAX] =3D { + [R_CONF] =3D (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | + CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), + [R_CE_CTRL] =3D 0x0000aa00, + [R_CTRL0] =3D 0x406b0641, + [R_CTRL1] =3D 0x00000400, + [R_CTRL2] =3D 0x00000400, + [R_CTRL3] =3D 0x00000400, + [R_SEG_ADDR0] =3D 0x08000000, + [R_SEG_ADDR1] =3D 0x10000800, + [R_SEG_ADDR2] =3D 0x00000000, + [R_SEG_ADDR3] =3D 0x00000000, + [R_DUMMY_DATA] =3D 0x00010000, + [R_DMA_DRAM_ADDR_HIGH] =3D 0x00000000, + [R_TIMINGS] =3D 0x007b0000, +}; + +static const MemoryRegionOps aspeed_2700_smc_flash_ops =3D { + .read =3D aspeed_smc_flash_read, + .write =3D aspeed_smc_flash_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + +static const AspeedSegments aspeed_2700_fmc_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kerne= l */ + { 256 * MiB, 128 * MiB }, /* default is disabled but needed for -kerne= l */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_2700_fmc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 2700 FMC Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 3; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 3; + asc->segments =3D aspeed_2700_fmc_segments; + asc->segment_addr_mask =3D 0xffffffff; + asc->resets =3D aspeed_2700_fmc_resets; + asc->flash_window_base =3D 0x100000000; + asc->flash_window_size =3D 1 * GiB; + asc->features =3D ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH; + asc->dma_flash_mask =3D 0x2FFFFFFC; + asc->dma_dram_mask =3D 0xFFFFFFFC; + asc->dma_start_length =3D 1; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_2700_smc_flash_ops; +} + +static const TypeInfo aspeed_2700_fmc_info =3D { + .name =3D "aspeed.fmc-ast2700", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_2700_fmc_class_init, +}; + +static const AspeedSegments aspeed_2700_spi0_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 128 * MiB, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_2700_spi0_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 2700 SPI0 Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 2; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 2; + asc->segments =3D aspeed_2700_spi0_segments; + asc->segment_addr_mask =3D 0xffffffff; + asc->flash_window_base =3D 0x180000000; + asc->flash_window_size =3D 1 * GiB; + asc->features =3D ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH; + asc->dma_flash_mask =3D 0x2FFFFFFC; + asc->dma_dram_mask =3D 0xFFFFFFFC; + asc->dma_start_length =3D 1; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_2700_smc_flash_ops; +} + +static const TypeInfo aspeed_2700_spi0_info =3D { + .name =3D "aspeed.spi0-ast2700", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_2700_spi0_class_init, +}; + +static const AspeedSegments aspeed_2700_spi1_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_2700_spi1_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 2700 SPI1 Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 2; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 2; + asc->segments =3D aspeed_2700_spi1_segments; + asc->segment_addr_mask =3D 0xffffffff; + asc->flash_window_base =3D 0x200000000; + asc->flash_window_size =3D 1 * GiB; + asc->features =3D ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH; + asc->dma_flash_mask =3D 0x2FFFFFFC; + asc->dma_dram_mask =3D 0xFFFFFFFC; + asc->dma_start_length =3D 1; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_2700_smc_flash_ops; +} + +static const TypeInfo aspeed_2700_spi1_info =3D { + .name =3D "aspeed.spi1-ast2700", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_2700_spi1_class_init, +}; + +static const AspeedSegments aspeed_2700_spi2_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_2700_spi2_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 2700 SPI2 Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 2; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 2; + asc->segments =3D aspeed_2700_spi2_segments; + asc->segment_addr_mask =3D 0xffffffff; + asc->flash_window_base =3D 0x280000000; + asc->flash_window_size =3D 1 * GiB; + asc->features =3D ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH; + asc->dma_flash_mask =3D 0x0FFFFFFC; + asc->dma_dram_mask =3D 0xFFFFFFFC; + asc->dma_start_length =3D 1; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_2700_smc_flash_ops; +} + +static const TypeInfo aspeed_2700_spi2_info =3D { + .name =3D "aspeed.spi2-ast2700", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_2700_spi2_class_init, +}; + static void aspeed_smc_register_types(void) { type_register_static(&aspeed_smc_flash_info); @@ -1954,6 +2182,10 @@ static void aspeed_smc_register_types(void) type_register_static(&aspeed_1030_fmc_info); type_register_static(&aspeed_1030_spi1_info); type_register_static(&aspeed_1030_spi2_info); + type_register_static(&aspeed_2700_fmc_info); + type_register_static(&aspeed_2700_spi0_info); + type_register_static(&aspeed_2700_spi1_info); + type_register_static(&aspeed_2700_spi2_info); } =20 type_init(aspeed_smc_register_types) --=20 2.25.1