From nobody Mon Nov 25 07:43:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1717480118; cv=none; d=zohomail.com; s=zohoarc; b=GWzWQrPsmVfaoMECbh9HQV78AH3CNrngpxVSKNWiSHnF7bhpaeCOCflu6CntNKLCdDf6KBU6A3Tr11/m4f8PVdejshqgDWNlQ7BuCe4P47UOT48HQGwx5UjjzfPqBeNCYbSSwSnB497lJfC224iexfLEJ5SRAX2UiyV03uqjbqc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717480118; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=7nDFQiXLK68Pv5NZC2TfS7ZlDHvUlSf4fovInTilKMI=; b=c7HdLd2P7trAVIIBd3TXDAUafZqfPwHpgx6udY4GoDlVzFCLbED+/UNquTTZMUSHDASgGp8ijL9Sm5HI7ISY++EVt+QkEbizeZqAVN9D8iL01E+D+1LqY1UeSRjjoCuZGZ8FvMcf+xWH8Rt5c3FLdCbHPh6T4lMCqVNvHfWHui4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1717480118364477.20504593744306; Mon, 3 Jun 2024 22:48:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sEMz0-0005s2-Ch; Tue, 04 Jun 2024 01:45:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEMyy-0005nP-6c; Tue, 04 Jun 2024 01:45:16 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEMyw-0008TH-C5; Tue, 04 Jun 2024 01:45:15 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 4 Jun 2024 13:44:43 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 4 Jun 2024 13:44:43 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , Alistair Francis , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v5 09/17] aspeed/smc: support different memory region ops for SMC flash region Date: Tue, 4 Jun 2024 13:44:30 +0800 Message-ID: <20240604054438.3424349-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240604054438.3424349-1-jamin_lin@aspeedtech.com> References: <20240604054438.3424349-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1717480120096100003 Content-Type: text/plain; charset="utf-8" It set "aspeed_smc_flash_ops" struct which containing read and write callbacks to be used when I/O is performed on the SMC flash region. And it set the valid max_access_size 4 by default for all ASPEED SMC models. However, the valid max_access_size 4 only support 32 bits CPUs. To support all ASPEED SMC model, introduce a new "const MemoryRegionOps *" attribute in AspeedSMCClass and use it in aspeed_smc_flash_realize function. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 14 +++++++++++++- include/hw/ssi/aspeed_smc.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index df0c63469c..129d06690d 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -1316,7 +1316,7 @@ static void aspeed_smc_flash_realize(DeviceState *dev= , Error **errp) * Use the default segment value to size the memory region. This * can be changed by FW at runtime. */ - memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops, + memory_region_init_io(&s->mmio, OBJECT(s), s->asc->reg_ops, s, name, s->asc->segments[s->cs].size); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); } @@ -1391,6 +1391,7 @@ static void aspeed_2400_smc_class_init(ObjectClass *k= lass, void *data) asc->segment_to_reg =3D aspeed_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_2400_smc_info =3D { @@ -1441,6 +1442,7 @@ static void aspeed_2400_fmc_class_init(ObjectClass *k= lass, void *data) asc->segment_to_reg =3D aspeed_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_2400_fmc_info =3D { @@ -1480,6 +1482,7 @@ static void aspeed_2400_spi1_class_init(ObjectClass *= klass, void *data) asc->reg_to_segment =3D aspeed_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_smc_dma_ctrl; asc->addr_width =3D aspeed_2400_spi1_addr_width; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_2400_spi1_info =3D { @@ -1525,6 +1528,7 @@ static void aspeed_2500_fmc_class_init(ObjectClass *k= lass, void *data) asc->segment_to_reg =3D aspeed_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_2500_fmc_info =3D { @@ -1560,6 +1564,7 @@ static void aspeed_2500_spi1_class_init(ObjectClass *= klass, void *data) asc->segment_to_reg =3D aspeed_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_2500_spi1_info =3D { @@ -1595,6 +1600,7 @@ static void aspeed_2500_spi2_class_init(ObjectClass *= klass, void *data) asc->segment_to_reg =3D aspeed_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_2500_spi2_info =3D { @@ -1682,6 +1688,7 @@ static void aspeed_2600_fmc_class_init(ObjectClass *k= lass, void *data) asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_2600_fmc_info =3D { @@ -1721,6 +1728,7 @@ static void aspeed_2600_spi1_class_init(ObjectClass *= klass, void *data) asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_2600_spi1_info =3D { @@ -1761,6 +1769,7 @@ static void aspeed_2600_spi2_class_init(ObjectClass *= klass, void *data) asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_2600_spi2_info =3D { @@ -1843,6 +1852,7 @@ static void aspeed_1030_fmc_class_init(ObjectClass *k= lass, void *data) asc->segment_to_reg =3D aspeed_1030_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_1030_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_1030_fmc_info =3D { @@ -1881,6 +1891,7 @@ static void aspeed_1030_spi1_class_init(ObjectClass *= klass, void *data) asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_1030_spi1_info =3D { @@ -1918,6 +1929,7 @@ static void aspeed_1030_spi2_class_init(ObjectClass *= klass, void *data) asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; + asc->reg_ops =3D &aspeed_smc_flash_ops; } =20 static const TypeInfo aspeed_1030_spi2_info =3D { diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index d305ce2e2f..234dca32b0 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -115,6 +115,7 @@ struct AspeedSMCClass { AspeedSegments *seg); void (*dma_ctrl)(AspeedSMCState *s, uint32_t value); int (*addr_width)(const AspeedSMCState *s); + const MemoryRegionOps *reg_ops; }; =20 #endif /* ASPEED_SMC_H */ --=20 2.25.1