From nobody Mon Nov 25 04:22:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1717431032; cv=none; d=zohomail.com; s=zohoarc; b=gVnjdHKHJKY7k2skJJHi3zwRym8+TLVvG4ySami6ScpwiYFubu+BrNIP+G38kzkvjsELxLXUD6XifHcefhxax5M30P89tXWcO1LiyLMUtKvA6Mfqb8lnzds1zmLm2/mDb+esw/dbM8oUfwGzxAHGkqJK1t4VLXAbIBhryTnpdvM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717431032; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dAmag+cWpcLwhgu5cuQHENQ1h6AJ+A+dNV70xL+L7j4=; b=H619Otm4X3lg8xVHJLmQcm/x4YNtm+m6plbL/SJSbR7mF2rwxYUGC49wAdaLmhMHgKnaDH+QhHHuG/YNWS0wRQGaqgY+Xys0+HdSQSDNlge7BjLSVwzdQmzi91r5uPUvm3Kx7Yu0AFQqwYOCTV1m3BQ3zM8w11MHwvGUi57VdA0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1717431032649127.83932670838965; Mon, 3 Jun 2024 09:10:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sEAFl-00020j-GB; Mon, 03 Jun 2024 12:09:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEAFh-000205-DG for qemu-devel@nongnu.org; Mon, 03 Jun 2024 12:09:41 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sEAFe-0000Z5-Qy for qemu-devel@nongnu.org; Mon, 03 Jun 2024 12:09:40 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-42134bb9735so21458805e9.1 for ; Mon, 03 Jun 2024 09:09:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35dd0649fb5sm8975858f8f.94.2024.06.03.09.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 09:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717430975; x=1718035775; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dAmag+cWpcLwhgu5cuQHENQ1h6AJ+A+dNV70xL+L7j4=; b=iVIIDOHVmhZt/q2pxqYjt5evBNfqYdAmv/gY5fDEjx/mZZc1SNs4IdsZR8f7zWCHh3 gRAcZ1MtkdbCInNw7dNTnUfkTgZPT+ZSGX/zb+Ih16WsAkmGvNSun6C7GMH9ZOWR8jyj L+rpTmTF+Z8i5eVqzDQb32um27MxTCnRhJ4XVES22Ns+YSqKtzddc+OrpQcJ9g4fPFpJ Cs/FeB3wwF0KkWHianmsi3SmCHzVJYgtF99JgDO/HR6AbJqknVvrEHE01P+arvSzvwNV IubM0GbD/+ewsqh17uybRkoDxyHjJgtMm8BlxLALOb/rz5tOA4w2L/JKTyCw5N20k1Bf tGfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717430975; x=1718035775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dAmag+cWpcLwhgu5cuQHENQ1h6AJ+A+dNV70xL+L7j4=; b=iNxOlAEFnl0vAUBfOvRarRV9PJ57NObn7Ze6Vl++i1PxO7ZL61d9DQfcpKQ9xA3mtv dCXjp/h65ZG/6mVEyqbG/uP/iEUKwJSjw7Y6OjseDZxJLxSPKM8Np8Eh8J95qBKv4+Ed wjkjaYLUN0mPjFTOwH35Sqolsmtrgrcb7jA4EmHmD5YeGu322vfEcAuNILhV05ey8Onr OVJnNHkw+Uwg1LJ8Jds96eCiI0LPv3vYXNoMQG3MHIWrLfXDkl2uYoDDJKdPwOY39ABL sfQox2lwn9OfIu9Fu1xC1P0oR0kFnikxqiHLcaSKu0HhhfL1eIS/sfeIyLGnQhYVTLGr H2SQ== X-Gm-Message-State: AOJu0Yw/1wrBdSunSlsPR+5YT3Tfp3sX/fR7qYilqbiIQGTCuIg9BGhS 0z7hDC9hndN9q2eds33NpYW7wS5amR0BYNWNi7lZEc8+EounKEnSp/o5BnFYGgdKMrxxkCp6WC7 U X-Google-Smtp-Source: AGHT+IEo9I+QgwyFPpE8UA7gzFvqqxv3KT56TJX4vzSME6jkm8uH/eng2IRzAkRjJofkLBj1UgtwmA== X-Received: by 2002:a05:600c:4e8b:b0:421:3a41:5428 with SMTP id 5b1f17b1804b1-4213a4157bcmr28421855e9.41.1717430975395; Mon, 03 Jun 2024 09:09:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 1/3] target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() Date: Mon, 3 Jun 2024 17:09:31 +0100 Message-Id: <20240603160933.1141717-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240603160933.1141717-1-peter.maydell@linaro.org> References: <20240603160933.1141717-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1717431033448100002 Content-Type: text/plain; charset="utf-8" In commit a96edb687e76 we set the cpu_exec_halt field of the TCGCPUOps arm_tcg_ops to arm_cpu_exec_halt(), but we left the arm_v7m_tcg_ops struct unchanged. That isn't wrong, because for M-profile FEAT_WFxT doesn't exist and the default handling for "no cpu_exec_halt method" is correct, but it's perhaps a little confusing. We would also like to make setting the cpu_exec_halt method mandatory. Initialize arm_v7m_tcg_ops cpu_exec_halt to the same function we use for A-profile. (On M-profile we never set up the wfxt timer so there is no change in behaviour here.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/internals.h | 3 +++ target/arm/cpu.c | 2 +- target/arm/tcg/cpu-v7m.c | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 11b5da2562f..e45ccd983e1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -364,6 +364,9 @@ void arm_restore_state_to_opc(CPUState *cs, =20 #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); + +/* Our implementation of TCGCPUOps::cpu_exec_halt */ +bool arm_cpu_exec_halt(CPUState *cs); #endif /* CONFIG_TCG */ =20 typedef enum ARMFPRounding { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 35fa281f1b9..948e904bd8a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1133,7 +1133,7 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs) } =20 #ifdef CONFIG_TCG -static bool arm_cpu_exec_halt(CPUState *cs) +bool arm_cpu_exec_halt(CPUState *cs) { bool leave_halt =3D cpu_has_work(cs); =20 diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index c059c681e94..5496f14dc16 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -244,6 +244,7 @@ static const TCGCPUOps arm_v7m_tcg_ops =3D { #else .tlb_fill =3D arm_cpu_tlb_fill, .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, + .cpu_exec_halt =3D arm_cpu_exec_halt, .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, --=20 2.34.1 From nobody Mon Nov 25 04:22:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1717431032; cv=none; d=zohomail.com; s=zohoarc; b=ii255vUaltomFLkLWT0IcQNirF7HzHtUGc733JSjfcvy9mBQBG+/J4gRMW8rsRCT32ys3mnjy6ivBSNfIba8qm6jiybAFWaKy98QwDpJ7Is8HZkpxyQKT0MtwgkfTrJgWMxVDm2uqKTBOuhsNR2RNXZmzcMZcoaXP085YdfonXY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1717431032; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZBdzLZZL/nRHExmbsGOFpgP9JHwy15yfEoxuNTlxcfY=; b=NYDbOSHBSDfY72R9SLdVtwLvN4DM5jhha9lLI9IS4MY4E3eTqtcVLQs2FU0ziZoDElbVvlt272OmFgOcvvUUH68c07qSGU+/DVqXb0GZfpTjGEbA4vsZy3N5lPN8XiGNKiIBGNxvduL4SFYF5e+212i/N+QyEX80Ye9blVGIYEU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1717431032380897.2421822653167; Mon, 3 Jun 2024 09:10:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sEAFt-00025n-QA; Mon, 03 Jun 2024 12:09:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sEAFj-00020k-Ue for qemu-devel@nongnu.org; Mon, 03 Jun 2024 12:09:45 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sEAFe-0000ZB-RT for qemu-devel@nongnu.org; Mon, 03 Jun 2024 12:09:41 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-35dc36b107fso3488284f8f.1 for ; Mon, 03 Jun 2024 09:09:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35dd0649fb5sm8975858f8f.94.2024.06.03.09.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 09:09:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717430976; x=1718035776; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZBdzLZZL/nRHExmbsGOFpgP9JHwy15yfEoxuNTlxcfY=; b=Xwfue4J4xH1fe0q7thdxHIDzGL3WnNxX2sRi1LHyafVCYneaczVDANL++w2djChePh xyuEnOMgJn7Tx21OedfB1qcQ7wNqpNeAlJfZLY8Mgllws9d5swDOhJJVsPnfMBBKcRDl pv9DRPJlhRr5FzNV4tv0eZh4B8MBp96FN+GW3w2oEuf30qclFnrXvl9TWPZ521UEl4Zx fxGoxKsnF3N8YnYIyliPn0+nbWBqArm6LkDn9tGLoYi8xgfow6vhx703g9xaUCe3IwKG Uo/OAlbYYODYWDDu3STX8nb/ZMuqxEYocVF/4fpIPEBDKcLTDPryCXgRr0Mq6swcVzSB 5cow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717430976; x=1718035776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZBdzLZZL/nRHExmbsGOFpgP9JHwy15yfEoxuNTlxcfY=; b=iPzdHxmG50WV96vQ9Oo3LxmEzjFfY2d8q0duiuyxsrZA68Pqk41Pjf+VrlUPqRCJ9v j3GkZKaAF/FG+9lhJlKusPyDfDCrbSTupmJe+2chf0ItGEJ3PTlYggwztGLl3NqF4+lY 9mrldrq+nZxdEMHqVIeI41dlTZ5OiiFPpFxI/jNF3Cu11dJFKd5PyeCqigYrVv/zSC1Q bJnQITmqZDx2jolHt+8yLOPipgr04l2/QWrvoImorlsiHxIkOUu1JoRykdHwfNrz360t TMnFck32xIZWEckYZDaE52lqZ3a4yBZs1nmccAG+o7ksPHjMBswkU0fxxg+FG0/RQuR0 2QnQ== X-Gm-Message-State: AOJu0YwW11RuwEaQBqlyCgw/kVvuOthYeHhg4r0m/Q3boynWfNT4IRgl iTuLw0BbWRWkwaBDh5QEofmi+6YUrsvCxdVhmkD5OwCtkO5BqQsWmzLAyuwrP8c3d38AzOKMYsu V X-Google-Smtp-Source: AGHT+IGr7PFyNJbVQYID1zYUbne+qCaVhI4/8MvGuvsUhD5+UfshJpby7+5t271WNICfOqORL2jIHw== X-Received: by 2002:adf:efca:0:b0:354:dde0:97a5 with SMTP id ffacd0b85a97d-35e0f27420emr6187169f8f.19.1717430975885; Mon, 03 Jun 2024 09:09:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 2/3] target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation Date: Mon, 3 Jun 2024 17:09:32 +0100 Message-Id: <20240603160933.1141717-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240603160933.1141717-1-peter.maydell@linaro.org> References: <20240603160933.1141717-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1717431033411100001 Content-Type: text/plain; charset="utf-8" Currently the TCGCPUOps::cpu_exec_halt method is optional, and if it is not set then the default is to call the CPUClass::has_work method (which has an identical function signature). We would like to make the cpu_exec_halt method mandatory so we can remove the runtime check and fallback handling. In preparation for that, make all the targets which don't need special handling in their cpu_exec_halt set it to their cpu_has_work implementation instead of leaving it unset. (This is every target except for arm and i386.) In the riscv case this requires us to make the function not be local to the source file it's defined in. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/riscv/internals.h | 3 +++ target/alpha/cpu.c | 1 + target/avr/cpu.c | 1 + target/cris/cpu.c | 2 ++ target/hppa/cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 2 ++ target/riscv/cpu.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 ++ target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/xtensa/cpu.c | 1 + 18 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 8239ae83ccc..0ac17bc5adb 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -136,4 +136,7 @@ static inline float16 check_nanbox_h(CPURISCVState *env= , uint64_t f) } } =20 +/* Our implementation of CPUClass::has_work */ +bool riscv_cpu_has_work(CPUState *cs); + #endif diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 0e2fbcb397f..9db1dffc03e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -219,6 +219,7 @@ static const TCGCPUOps alpha_tcg_ops =3D { #else .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, + .cpu_exec_halt =3D alpha_cpu_has_work, .do_interrupt =3D alpha_cpu_do_interrupt, .do_transaction_failed =3D alpha_cpu_do_transaction_failed, .do_unaligned_access =3D alpha_cpu_do_unaligned_access, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f53e1192b15..3132842d565 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -210,6 +210,7 @@ static const TCGCPUOps avr_tcg_ops =3D { .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .restore_state_to_opc =3D avr_restore_state_to_opc, .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, + .cpu_exec_halt =3D avr_cpu_has_work, .tlb_fill =3D avr_cpu_tlb_fill, .do_interrupt =3D avr_cpu_do_interrupt, }; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 535ec39c730..ff31ca7fbc1 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -186,6 +186,7 @@ static const TCGCPUOps crisv10_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D cris_cpu_tlb_fill, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, + .cpu_exec_halt =3D cris_cpu_has_work, .do_interrupt =3D crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; @@ -197,6 +198,7 @@ static const TCGCPUOps crisv32_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D cris_cpu_tlb_fill, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, + .cpu_exec_halt =3D cris_cpu_has_work, .do_interrupt =3D cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index f0507874ce6..7cf2e2f266d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -228,6 +228,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D hppa_cpu_tlb_fill, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, + .cpu_exec_halt =3D hppa_cpu_has_work, .do_interrupt =3D hppa_cpu_do_interrupt, .do_unaligned_access =3D hppa_cpu_do_unaligned_access, .do_transaction_failed =3D hppa_cpu_do_transaction_failed, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b5c1ec94af5..70b41807c8d 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -736,6 +736,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D loongarch_cpu_tlb_fill, .cpu_exec_interrupt =3D loongarch_cpu_exec_interrupt, + .cpu_exec_halt =3D loongarch_cpu_has_work, .do_interrupt =3D loongarch_cpu_do_interrupt, .do_transaction_failed =3D loongarch_cpu_do_transaction_failed, #endif diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index efd6bbded86..1d49f4cb238 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -536,6 +536,7 @@ static const TCGCPUOps m68k_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D m68k_cpu_tlb_fill, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, + .cpu_exec_halt =3D m68k_cpu_has_work, .do_interrupt =3D m68k_cpu_do_interrupt, .do_transaction_failed =3D m68k_cpu_transaction_failed, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 41ad47d04cb..135947ee800 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -413,6 +413,7 @@ static const TCGCPUOps mb_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D mb_cpu_tlb_fill, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, + .cpu_exec_halt =3D mb_cpu_has_work, .do_interrupt =3D mb_cpu_do_interrupt, .do_transaction_failed =3D mb_cpu_transaction_failed, .do_unaligned_access =3D mb_cpu_do_unaligned_access, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bbe01d07dd8..89655b1900f 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -555,6 +555,7 @@ static const TCGCPUOps mips_tcg_ops =3D { #if !defined(CONFIG_USER_ONLY) .tlb_fill =3D mips_cpu_tlb_fill, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, + .cpu_exec_halt =3D mips_cpu_has_work, .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, .do_unaligned_access =3D mips_cpu_do_unaligned_access, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fdaaa09fc87..6ec54ad7a6c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -233,6 +233,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D openrisc_cpu_tlb_fill, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, + .cpu_exec_halt =3D openrisc_cpu_has_work, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 01e358a4a5a..cdada7987d8 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1,3 +1,4 @@ + /* * PowerPC CPU initialization for qemu. * @@ -7481,6 +7482,7 @@ static const TCGCPUOps ppc_tcg_ops =3D { #else .tlb_fill =3D ppc_cpu_tlb_fill, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, + .cpu_exec_halt =3D ppc_cpu_has_work, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, .cpu_exec_exit =3D ppc_cpu_exec_exit, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb1a2e7d6d9..54e12eed466 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -896,7 +896,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } =20 -static bool riscv_cpu_has_work(CPUState *cs) +bool riscv_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY RISCVCPU *cpu =3D RISCV_CPU(cs); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 40054a391a6..643f9a224b8 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -21,6 +21,7 @@ #include "exec/exec-all.h" #include "tcg-cpu.h" #include "cpu.h" +#include "internals.h" #include "pmu.h" #include "time_helper.h" #include "qapi/error.h" @@ -137,6 +138,7 @@ static const TCGCPUOps riscv_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D riscv_cpu_tlb_fill, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, + .cpu_exec_halt =3D riscv_cpu_has_work, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 8a584f0a111..36d2a6f1890 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -192,6 +192,7 @@ static const TCGCPUOps rx_tcg_ops =3D { =20 #ifndef CONFIG_USER_ONLY .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, + .cpu_exec_halt =3D rx_cpu_has_work, .do_interrupt =3D rx_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 2bbeaca36e4..0fbfcd35d83 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -370,6 +370,7 @@ static const TCGCPUOps s390_tcg_ops =3D { #else .tlb_fill =3D s390_cpu_tlb_fill, .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, + .cpu_exec_halt =3D s390_cpu_has_work, .do_interrupt =3D s390_cpu_do_interrupt, .debug_excp_handler =3D s390x_cpu_debug_excp_handler, .do_unaligned_access =3D s390x_cpu_do_unaligned_access, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 618aa7154ed..8f07261dcfd 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -254,6 +254,7 @@ static const TCGCPUOps superh_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D superh_cpu_tlb_fill, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, + .cpu_exec_halt =3D superh_cpu_has_work, .do_interrupt =3D superh_cpu_do_interrupt, .do_unaligned_access =3D superh_cpu_do_unaligned_access, .io_recompile_replay_branch =3D superh_io_recompile_replay_branch, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 5be1592e66a..87f0b4a6c05 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -914,6 +914,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D sparc_cpu_tlb_fill, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, + .cpu_exec_halt =3D sparc_cpu_has_work, .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, .do_unaligned_access =3D sparc_cpu_do_unaligned_access, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index de907cfeb1b..a08c7a0b1f2 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -234,6 +234,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D xtensa_cpu_tlb_fill, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, + .cpu_exec_halt =3D xtensa_cpu_has_work, .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, --=20 2.34.1 From nobody Mon Nov 25 04:22:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35dd0649fb5sm8975858f8f.94.2024.06.03.09.09.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 09:09:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717430976; x=1718035776; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B+y2VUAaODGRx6I5aA9+iua3n6PE+xKIoh7aOmqQq9M=; b=LGshqUeL/1fb2cUS0ALjPU2MUlJ2sRnTHc2qQa0Tyfh3kTwFCNhlHrRLraRt4nDnyP tatm/bVL9NurrIS2NQ6Mqz0lkSxzlei27SBDQFZj57cl8Sf2y/jli+uMesa8RXdLkdN8 THy8m11wjPW31dHXftNL09LY9rfzyWgaE8yE3hJW3iDw6tHObKr0+TKp+/PA6ynRoH6Q dR6Ess3iaAKpsw/EzYySP43z4ywGhnHplrgpl+A6PV3afGIpuVznyqWQDVq54743PFSf 2W6bDjqG3HdAS7lbd9p8oAZd+j7Fu2V3bl7sYt2hWzAa1FONSZ9Hx7d6HQy9fFd83siz oCow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717430976; x=1718035776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B+y2VUAaODGRx6I5aA9+iua3n6PE+xKIoh7aOmqQq9M=; b=GmTvLmc8loq2Mc9byrJsJ3U+UI9BJdQOgkW+tVZ0B9t7l+3kb/dr2L8irK8bBGXKs2 LR6X+oi6KgNj3Suk8lln1XqDoqEyPe7lCMVeyWnnwRgLoXeRUvq7n4IADTYH8a6f4fQT zugNSu1dXu1lt+5TM+XPwFfQL7YT1Bt2wb1MQn7ER6SKkvmz0DUFh6yIwMJcNy8+qp2b EBfmWJyLj56WRKJHJlQpUj1+MzrgrH7ms129H7eW2GCpMe3TZYvrak31/v6mjNZV1OQQ /ZxVztUgYZAoWFchVNqS91uGQwWooN94WFNR4THm8ReonhxgP3oXSRniiTdNDngsbfgr EnnA== X-Gm-Message-State: AOJu0YwtlNjyCCxbfqJQqH558AqR1bs4aDPunwnylM/aAzMmsvUEBi9v +1Y0fTE3SM1Lrl6nTY84tT7fKgytp0d5RsGjQrk797Ly6kQeE/NXnvDLafcI/42A60wk3ftE4i0 i X-Google-Smtp-Source: AGHT+IGfkuAGvac7mXyR0LWyUEdUCK2v84cqTqDJiP/QGmCOk5s6a5BJ9q3LbjiJl8UeGA/oDBRN0w== X-Received: by 2002:ac2:4853:0:b0:52b:8877:30f2 with SMTP id 2adb3069b0e04-52b8980aca3mr5781191e87.59.1717430976365; Mon, 03 Jun 2024 09:09:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 3/3] accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory Date: Mon, 3 Jun 2024 17:09:33 +0100 Message-Id: <20240603160933.1141717-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240603160933.1141717-1-peter.maydell@linaro.org> References: <20240603160933.1141717-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1717431071599100003 Content-Type: text/plain; charset="utf-8" Now that all targets set TCGCPUOps::cpu_exec_halt, we can make it mandatory and remove the fallback handling that calls cpu_has_work. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 9 ++++++--- accel/tcg/cpu-exec.c | 7 +------ 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 099de3375e3..34318cf0e60 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -122,10 +122,13 @@ struct TCGCPUOps { * to do when the CPU is in the halted state. * * Return true to indicate that the CPU should now leave halt, false - * if it should remain in the halted state. + * if it should remain in the halted state. (This should generally + * be the same value that cpu_has_work() would return.) * - * If this method is not provided, the default is to do nothing, and - * to leave halt if cpu_has_work() returns true. + * This method must be provided. If the target does not need to + * do anything special for halt, the same function used for its + * CPUClass::has_work method can be used here, as they have the + * same function signature. */ bool (*cpu_exec_halt)(CPUState *cpu); /** diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 6711b58e0b2..8be4d2a1330 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -682,13 +682,8 @@ static inline bool cpu_handle_halt(CPUState *cpu) #ifndef CONFIG_USER_ONLY if (cpu->halted) { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; - bool leave_halt; + bool leave_halt =3D tcg_ops->cpu_exec_halt(cpu); =20 - if (tcg_ops->cpu_exec_halt) { - leave_halt =3D tcg_ops->cpu_exec_halt(cpu); - } else { - leave_halt =3D cpu_has_work(cpu); - } if (!leave_halt) { return true; } --=20 2.34.1