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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6323e18c7sm62375435ad.177.2024.06.03.04.18.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jun 2024 04:18:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717413497; x=1718018297; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=okL/u9Yr4I1gdpYP+OUmz0dGlxU1P8AIMDXGmwEB0cY=; b=DmNQcPw9JMc7Zjf7bAm5ShfxecBWkiYyYza9zBgBdRvtz7PAC+cCEDAoOacwLEs5PW aq2ClBxCBRDQUymOJZP+Cd1U52/BqgdY25nDtbFgd6G7iT5Dc8n1ySIQsZR0uUS83HT6 MDlxxsLW1aBmp75EE9BqQpSZqhkzPo9JG8UGXHPBQ4KWOf1Yeu4m/DJGhgC5M15BkHh0 HWBWEzxkJDi9Dhi/MClpEWy1HYcg2615skm0lz5R7Fc9i1xg/IQwveT/a7RR0TWw/n0e QiY8jlko/yyxlJkuv+WtAQdvgAowZtLzxp4LEGCrvoZECd2+Fopy2hgxND/cDA/s2d3C gycw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717413497; x=1718018297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=okL/u9Yr4I1gdpYP+OUmz0dGlxU1P8AIMDXGmwEB0cY=; b=tPxO6NMFRyIEEOheYw9xKzhmw5xNf9taeWiE6qRNp6DnDjDtmNrwleF0EcAt/8Cleg kcla8pGZQ8aVL3ajmLOl77Rhp7NGGW/lMzCQ6ivJ7rYpthZwSD4rbOGMB3gHCnh4xvKU ceornvnP94BJZQO9LPWez/qkwdbiyPd8ejCByYVxUA8gF2RgLUMVhdhep/hLPFrQAcYB J63Mqb1tKRH9PQvr6NA76M6Ufwrvvy9zSqQ8ztOskr4XIWnBnFiUmnmuz/P2RwXoW5Sz /rfqNotYWdBS658+npnkynHXBkW3GR5QGHabk5RJU+hmFWjiuFw04c8TY3faJl9Pbbrp TKRw== X-Forwarded-Encrypted: i=1; AJvYcCW36U3uFmwywMM8Wmcc5qYo5vcscijERMwLG/4W1piFxAAHmfBVUj+4sPeCi1GZIZpM63uRIuyos1viQKNZLbkcahDhL7uK X-Gm-Message-State: AOJu0YzOec6wxoNraNpVuiDkCXaThfn1QMKEQ2BtREPQgLJtO+ibouiT XJ/bY/g8uuj6nI7qiMfGWFQtmJlne8JvUqR/AE//JDqkXBX2FInNqHTPXQ== X-Google-Smtp-Source: AGHT+IEwm17AaeWkVnSCEdgpsmu7Zlp9BB/vFh3ccCz8f25QhWn3K+LpdbcBjyy38V5B8kMNRoZEgw== X-Received: by 2002:a17:902:da86:b0:1f6:8dc8:184d with SMTP id d9443c01a7336-1f68dc81aeemr2121805ad.23.1717413496938; Mon, 03 Jun 2024 04:18:16 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yong-Xuan Wang , Andrew Jones , qemu-stable , Alistair Francis Subject: [PULL v2 25/27] target/riscv/kvm.c: Fix the hart bit setting of AIA Date: Mon, 3 Jun 2024 21:16:41 +1000 Message-ID: <20240603111643.258712-26-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240603111643.258712-1-alistair.francis@wdc.com> References: <20240603111643.258712-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1717413640890100004 Content-Type: text/plain; charset="utf-8" From: Yong-Xuan Wang In AIA spec, each hart (or each hart within a group) has a unique hart number to locate the memory pages of interrupt files in the address space. The number of bits required to represent any hart number is equal to ceil(log2(hmax + 1)), where hmax is the largest hart number among groups. However, if the largest hart number among groups is a power of 2, QEMU will pass an inaccurate hart-index-bit setting to Linux. For example, when the guest OS has 4 harts, only ceil(log2(3 + 1)) =3D 2 bits are sufficient to represent 4 harts, but we passes 3 to Linux. The code needs to be updated to ensure accurate hart-index-bit settings. Additionally, a Linux patch[1] is necessary to correctly recover the hart index when the guest OS has only 1 hart, where the hart-index-bit is 0. [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifiv= e.com/t/ Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones Cc: qemu-stable Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 473416649f..235e2cdaca 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine, uin= t64_t group_shift, } } =20 - hart_bits =3D find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; + + if (max_hart_per_socket > 1) { + max_hart_per_socket--; + hart_bits =3D find_last_bit(&max_hart_per_socket, BITS_PER_LONG) += 1; + } else { + hart_bits =3D 0; + } + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, &hart_bits, true, NULL); --=20 2.45.1