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Iglesias" , Alistair Francis , Peter Maydell , Jason Wang , qemu-arm@nongnu.org (open list:Xilinx Zynq), "Fea.Wang" Subject: [PATCH 1/4] hw/dma: Enhance error handling in loading description Date: Mon, 3 Jun 2024 13:52:45 +0800 Message-Id: <20240603055248.3928469-2-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240603055248.3928469-1-fea.wang@sifive.com> References: <20240603055248.3928469-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=fea.wang@sifive.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1717393753001100007 Content-Type: text/plain; charset="utf-8" Loading a description from memory may cause a bus-error. In this case, the DMA should stop working, set the error flag, and return the error value. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- hw/dma/xilinx_axidma.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 0ae056ed06..4b475e5484 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -71,8 +71,10 @@ enum { enum { DMASR_HALTED =3D 1, DMASR_IDLE =3D 2, + DMASR_SLVERR =3D 1 << 5, DMASR_IOC_IRQ =3D 1 << 12, DMASR_DLY_IRQ =3D 1 << 13, + DMASR_ERR_IRQ =3D 1 << 14, =20 DMASR_IRQ_MASK =3D 7 << 12 }; @@ -190,17 +192,27 @@ static inline int streamid_from_addr(hwaddr addr) return sid; } =20 -static void stream_desc_load(struct Stream *s, hwaddr addr) +static MemTxResult stream_desc_load(struct Stream *s, hwaddr addr) { struct SDesc *d =3D &s->desc; =20 - address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, sizeo= f *d); + MemTxResult result =3D address_space_read(&s->dma->as, + addr, MEMTXATTRS_UNSPECIFIED, + d, sizeof *d); + if (result !=3D MEMTX_OK) { + s->regs[R_DMACR] &=3D ~DMACR_RUNSTOP; + s->regs[R_DMASR] |=3D DMASR_HALTED; + s->regs[R_DMASR] |=3D DMASR_SLVERR; + s->regs[R_DMASR] |=3D DMASR_ERR_IRQ; + return result; + } =20 /* Convert from LE into host endianness. */ d->buffer_address =3D le64_to_cpu(d->buffer_address); d->nxtdesc =3D le64_to_cpu(d->nxtdesc); d->control =3D le32_to_cpu(d->control); d->status =3D le32_to_cpu(d->status); + return result; } =20 static void stream_desc_store(struct Stream *s, hwaddr addr) --=20 2.34.1