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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42129de0cf9sm37027685e9.13.2024.05.31.05.04.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 05:04:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717157071; x=1717761871; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WemVooe7jVrEZVThnl7qxXnfDDz1+XFheEherDLTAvE=; b=Tnz0NhFr91aXM67b/4qf4D8tVenpPKxSuKnWRWODAsdRo/qUqcD4NukyT2CrJgH+Wx alGufi/SmP2bAEzubPD65c2amkStCbW0/s9OXRYSVVt19lMKQplyo7PYm6DzUzWnr3/w fPAyjTcgR5JfrT12A9Wi798nBeBJ8D+aiVS1Ve9GLTdvsgzpN6+dl6+3Hub57ZWr5rlh Sbvvit48ffZ/SILBden+lo/TUcNaw1HR9TQx9v2wE8fVEXSY3NDzXYVGVm0CQbFbSq8s kK8giW9H6N/sKCo06rp0NUYkBy6zFPI12b3/MpEm01NEfLl51GK7AESwSG2x5rX23vLg tU8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717157071; x=1717761871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WemVooe7jVrEZVThnl7qxXnfDDz1+XFheEherDLTAvE=; b=fWFd7EjjFTVvwyfgPiwuu1vpky+X33qzXMqR1BK0ZZaeLrQXejLpZHol8tqovbNh24 /4Boxuw1zRP1V5aaJ+7bkOV+kKiZRVe1qD2oFIpvEqvJMi7+KHKLh2sq+fRVnc+en/E7 X4gWfwfsgg+Cn4xT+RZQ5A2d57H+K4ymFHnYCgm8q8L1qVVFhkp8HNPhCp1Tn3xUTQNQ WWktw37y4FCSpuPosmb6d6cJdXxnrGvOIcWlpc/9etiiKZgwsirI94Q/B2tW2DCISF1S syqUHNWhnjfFgNRrHWyrAsWO7CnLaifde4ppEolCRW5K644a9vBLOn2iIR/TF6CiDHL7 oQHA== X-Gm-Message-State: AOJu0Yyo2E92PEZ0I+7xQJwcD1OygUUKwuyXazTSzVy5gkpDIGLh2FDo aVPkxp6Laz6mTVt/hKvvl6yQns2XGPNgUOtBkAvZXYZ8/rc8MEtrj+fE1rvrcfkkARyE4FDmMzJ t X-Google-Smtp-Source: AGHT+IEzbPwfFhyA/4Ir5tlIYVPGVJFiYIAKkCSm2q04em7+JMRUmwKNwIBuCpX/mzj7ggOQuHDLOQ== X-Received: by 2002:a05:651c:499:b0:2ea:853f:18e4 with SMTP id 38308e7fff4ca-2ea950e5266mr10657301fa.13.1717157071012; Fri, 31 May 2024 05:04:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/43] target/arm: Disable SVE extensions when SVE is disabled Date: Fri, 31 May 2024 13:03:57 +0100 Message-Id: <20240531120401.394550-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240531120401.394550-1-peter.maydell@linaro.org> References: <20240531120401.394550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1717157182518100001 Content-Type: text/plain; charset="utf-8" From: Marcin Juszkiewicz Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304 Reported-by: Marcin Juszkiewicz Signed-off-by: Richard Henderson Signed-off-by: Marcin Juszkiewicz Message-id: 20240526204551.553282-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c15d086049f..862d2b92fa4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -109,7 +109,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * No explicit bits enabled, and no implicit bits from sve-max-vq. */ if (!cpu_isar_feature(aa64_sve, cpu)) { - /* SVE is disabled and so are all vector lengths. Good. */ + /* + * SVE is disabled and so are all vector lengths. Good. + * Disable all SVE extensions as well. + */ + cpu->isar.id_aa64zfr0 =3D 0; return; } =20 --=20 2.34.1