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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1717157433668100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20240528203044.612851-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 4 ++++ target/arm/tcg/translate-a64.c | 22 +++++++--------------- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index ea897d6732c..9e027760367 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -758,6 +758,8 @@ USQADD_s 0111 1110 ..1 00000 00111 0 ..... .....= @r2r_e =20 SSHL_s 0101 1110 111 ..... 01000 1 ..... ..... @rrr_d USHL_s 0111 1110 111 ..... 01000 1 ..... ..... @rrr_d +SRSHL_s 0101 1110 111 ..... 01010 1 ..... ..... @rrr_d +URSHL_s 0111 1110 111 ..... 01010 1 ..... ..... @rrr_d =20 ### Advanced SIMD scalar pairwise =20 @@ -882,6 +884,8 @@ USQADD_v 0.10 1110 ..1 00000 00111 0 ..... .....= @qr2r_e =20 SSHL_v 0.00 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e USHL_v 0.10 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e +SRSHL_v 0.00 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e +URSHL_v 0.10 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e =20 ### Advanced SIMD scalar x indexed element =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7e981f8d011..c751da78ef0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5116,6 +5116,8 @@ static bool do_int3_scalar_d(DisasContext *s, arg_rrr= _e *a, =20 TRANS(SSHL_s, do_int3_scalar_d, a, gen_sshl_i64) TRANS(USHL_s, do_int3_scalar_d, a, gen_ushl_i64) +TRANS(SRSHL_s, do_int3_scalar_d, a, gen_helper_neon_rshl_s64) +TRANS(URSHL_s, do_int3_scalar_d, a, gen_helper_neon_rshl_u64) =20 static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a, gen_helper_gvec_3_ptr * const fns[3]) @@ -5364,6 +5366,8 @@ TRANS(USQADD_v, do_gvec_fn3, a, gen_gvec_usqadd_qc) =20 TRANS(SSHL_v, do_gvec_fn3, a, gen_gvec_sshl) TRANS(USHL_v, do_gvec_fn3, a, gen_gvec_ushl) +TRANS(SRSHL_v, do_gvec_fn3, a, gen_gvec_srshl) +TRANS(URSHL_v, do_gvec_fn3, a, gen_gvec_urshl) =20 =20 /* @@ -9384,13 +9388,6 @@ static void handle_3same_64(DisasContext *s, int opc= ode, bool u, gen_helper_neon_qshl_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm); } break; - case 0xa: /* SRSHL, URSHL */ - if (u) { - gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm); - } else { - gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm); - } - break; case 0xb: /* SQRSHL, UQRSHL */ if (u) { gen_helper_neon_qrshl_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm); @@ -9409,6 +9406,7 @@ static void handle_3same_64(DisasContext *s, int opco= de, bool u, case 0x1: /* SQADD / UQADD */ case 0x5: /* SQSUB / UQSUB */ case 0x8: /* SSHL, USHL */ + case 0xa: /* SRSHL, URSHL */ g_assert_not_reached(); } } @@ -9433,7 +9431,6 @@ static void disas_simd_scalar_three_reg_same(DisasCon= text *s, uint32_t insn) case 0x9: /* SQSHL, UQSHL */ case 0xb: /* SQRSHL, UQRSHL */ break; - case 0xa: /* SRSHL, URSHL */ case 0x6: /* CMGT, CMHI */ case 0x7: /* CMGE, CMHS */ case 0x11: /* CMTST, CMEQ */ @@ -9453,6 +9450,7 @@ static void disas_simd_scalar_three_reg_same(DisasCon= text *s, uint32_t insn) case 0x1: /* SQADD, UQADD */ case 0x5: /* SQSUB, UQSUB */ case 0x8: /* SSHL, USHL */ + case 0xa: /* SRSHL, URSHL */ unallocated_encoding(s); return; } @@ -10929,6 +10927,7 @@ static void disas_simd_3same_int(DisasContext *s, u= int32_t insn) case 0x01: /* SQADD, UQADD */ case 0x05: /* SQSUB, UQSUB */ case 0x08: /* SSHL, USHL */ + case 0x0a: /* SRSHL, URSHL */ unallocated_encoding(s); return; } @@ -10938,13 +10937,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) } =20 switch (opcode) { - case 0x0a: /* SRSHL, URSHL */ - if (u) { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_urshl, size); - } else { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_srshl, size); - } - return; case 0x0c: /* SMAX, UMAX */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); --=20 2.34.1