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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [RFC v2 7/7] qemu-options: Add the cache topology description of -smp Date: Thu, 30 May 2024 18:15:39 +0800 Message-Id: <20240530101539.768484-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530101539.768484-1-zhao1.liu@intel.com> References: <20240530101539.768484-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.036, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1717063339953100004 Content-Type: text/plain; charset="utf-8" Signed-off-by: Zhao Liu --- Changes since RFC v1: * Use "*_cache=3Dtopo_level" as -smp example as the original "level" term for a cache has a totally different meaning. (Jonathan) --- qemu-options.hx | 50 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 8ca7f34ef0c8..29d8a4b9b68b 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -282,7 +282,8 @@ ERST DEF("smp", HAS_ARG, QEMU_OPTION_smp, "-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,drawers=3Ddrawers][,books=3Dbo= oks][,sockets=3Dsockets]\n" " [,dies=3Ddies][,clusters=3Dclusters][,modules=3Dmodule= s][,cores=3Dcores]\n" - " [,threads=3Dthreads]\n" + " [,threads=3Dthreads][,l1d-cache=3Dtopo_level][,l1i-cac= he=3Dtopo_level]\n" + " [,l2-cache=3Dtopo_level][,l3-cache=3Dtopo_level]\n" " set the number of initial CPUs to 'n' [default=3D1]\n" " maxcpus=3D maximum number of total CPUs, including\n" " offline CPUs for hotplug, etc\n" @@ -294,7 +295,11 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " modules=3D number of modules in one cluster\n" " cores=3D number of cores in one module\n" " threads=3D number of threads in one core\n" - "Note: Different machines may have different subsets of the CPU topolo= gy\n" + " l1d-cache=3D topology level of L1 D-cache\n" + " l1i-cache=3D topology level of L1 I-cache\n" + " l2-cache=3D topology level of L2 cache\n" + " l3-cache=3D topology level of L3 cache\n" + "Note: Different machines may have different subsets of the CPU and ca= che topology\n" " parameters supported, so the actual meaning of the supported pa= rameters\n" " will vary accordingly. For example, for a machine type that sup= ports a\n" " three-level CPU hierarchy of sockets/cores/threads, the paramet= ers will\n" @@ -308,7 +313,7 @@ DEF("smp", HAS_ARG, QEMU_OPTION_smp, " must be set as 1 in the purpose of correct parsing.\n", QEMU_ARCH_ALL) SRST -``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,drawers=3Ddrawers][,books=3Dbooks= ][,sockets=3Dsockets][,dies=3Ddies][,clusters=3Dclusters][,modules=3Dmodule= s][,cores=3Dcores][,threads=3Dthreads]`` +``-smp [[cpus=3D]n][,maxcpus=3Dmaxcpus][,drawers=3Ddrawers][,books=3Dbooks= ][,sockets=3Dsockets][,dies=3Ddies][,clusters=3Dclusters][,modules=3Dmodule= s][,cores=3Dcores][,threads=3Dthreads][,l1d-cache=3Dtopo_level][,l1i-cache= =3Dtopo_level][,l2-cache=3Dtopo_level][,l3-cache=3Dtopo_level]`` Simulate a SMP system with '\ ``n``\ ' CPUs initially present on the machine type board. On boards supporting CPU hotplug, the optional '\ ``maxcpus``\ ' parameter can be set to enable further CPUs to be @@ -322,15 +327,34 @@ SRST Both parameters are subject to an upper limit that is determined by the specific machine type chosen. =20 + CPU topology parameters include '\ ``drawers``\ ', '\ ``books``\ ', + '\ ``sockets``\ ', '\ ``dies``\ ', '\ ``clusters``\ ', '\ ``modules``\= ', + '\ ``cores``\ ' and '\ ``threads``\ '. These CPU parameters accept only + integers and are used to specify the number of specific topology domai= ns + under the corresponding topology level. + To control reporting of CPU topology information, values of the topolo= gy parameters can be specified. Machines may only support a subset of the - parameters and different machines may have different subsets supported - which vary depending on capacity of the corresponding CPU targets. So - for a particular machine type board, an expected topology hierarchy can + CPU topology parameters and different machines may have different subs= ets + supported which vary depending on capacity of the corresponding CPU ta= rgets. + So for a particular machine type board, an expected topology hierarchy= can be defined through the supported sub-option. Unsupported parameters can also be provided in addition to the sub-option, but their values must = be set as 1 in the purpose of correct parsing. =20 + Cache topology parameters include '\ ``l1d-cache``\ ', '\ ``l1i-cache`= `\ ', + '\ ``l2-cache``\ ' and '\ ``l3-cache``\ '. These cache topology parame= ters + accept the strings of CPU topology levels (such as '\ ``drawer``\ ', '= \ ``book``\ ', + '\ ``socket``\ ', '\ ``die``\ ', '\ ``cluster``\ ', '\ ``module``\ ', + '\ ``core``\ ' or '\ ``thread``\ '). Exactly which topology level stri= ngs + could be accepted as the parameter depends on the machine's support fo= r the + corresponding CPU topology level. + + Machines may also only support a subset of the cache topology paramete= rs. + Unsupported cache topology parameters will be omitted, and correspondi= ngly, + the target CPU's cache topology will use the its default cache topology + setting. + Either the initial CPU count, or at least one of the topology paramete= rs must be specified. The specified parameters must be greater than zero, explicit configuration like "cpus=3D0" is not allowed. Values for any @@ -356,6 +380,20 @@ SRST =20 -smp 32,sockets=3D2,dies=3D2,modules=3D2,cores=3D2,threads=3D2,max= cpus=3D32 =20 + The following sub-option defines a CPU topology hierarchy (2 sockets + totally on the machine, 2 dies per socket, 2 modules per die, 2 cores = per + module, 2 threads per core) with 3-level cache topology hierarchy (L1 + D-cache per core, L1 I-cache per core, L2 cache per core and L3 cache = per + die) for PC machines which support sockets/dies/modules/cores/threads. + Some members of the CPU topology option can be omitted but their values + will be automatically computed. Some members of the cache topology + option can also be omitted and target CPU will use the default topolog= y.: + + :: + + -smp 32,sockets=3D2,dies=3D2,modules=3D2,cores=3D2,threads=3D2,max= cpus=3D32,\ + l1d-cache=3Dcore,l1i-cache=3Dcore,l2-cache=3Dcore,l3-cache=3D= die + The following sub-option defines a CPU topology hierarchy (2 sockets totally on the machine, 2 clusters per socket, 2 cores per cluster, 2 threads per core) for ARM virt machines which support sockets/cluste= rs --=20 2.34.1