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Date: Wed, 29 May 2024 17:09:48 +0100 Message-Id: <20240529160950.132754-5-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240529160950.132754-1-rkanwal@rivosinc.com> References: <20240529160950.132754-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=rkanwal@rivosinc.com; helo=mail-lj1-x229.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1716999118674100030 This commit adds logic to records CTR entries of different types and adds required hooks in TCG and interrupt/Exception logic to record events. This commit also adds support to invoke freeze CTR logic for breakpoint exceptions and counter overflow interrupts. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 8 + target/riscv/cpu_helper.c | 206 ++++++++++++++++++ target/riscv/helper.h | 8 +- .../riscv/insn_trans/trans_privileged.c.inc | 6 +- target/riscv/insn_trans/trans_rvi.c.inc | 27 +++ target/riscv/op_helper.c | 112 +++++++++- target/riscv/translate.c | 9 + 7 files changed, 370 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3d4d5172b8..a294a5372a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -268,6 +268,10 @@ struct CPUArchState { uint32_t sctrstatus; uint64_t vsctrctl; =20 + uint64_t ctr_src[16 << SCTRDEPTH_MAX]; + uint64_t ctr_dst[16 << SCTRDEPTH_MAX]; + uint64_t ctr_data[16 << SCTRDEPTH_MAX]; + /* Machine and Supervisor interrupt priorities */ uint8_t miprio[64]; uint8_t siprio[64]; @@ -565,6 +569,10 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, in= t index, uint64_t bit); #endif void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool vir= t_en); =20 +void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask); +void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, + uint64_t type, target_ulong prev_priv, bool prev_= virt); + void riscv_translate_init(void); G_NORETURN void riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a441a03ef4..e064a7306e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -663,6 +663,10 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint= 64_t mask, uint64_t value) =20 BQL_LOCK_GUARD(); =20 + if (MIP_LCOFIP & value & mask) { + riscv_ctr_freeze(env, MCTRCTL_LCOFIFRZ); + } + env->mip =3D (env->mip & ~mask) | (value & mask); =20 riscv_cpu_interrupt(env); @@ -691,6 +695,197 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env= , uint32_t priv, } } =20 +void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask) +{ + assert((freeze_mask & (~(MCTRCTL_BPFRZ | MCTRCTL_LCOFIFRZ))) =3D=3D 0); + + if (env->mctrctl & freeze_mask) { + env->sctrstatus |=3D SCTRSTATUS_FROZEN; + } +} + +static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt) +{ + switch (priv) { + case PRV_M: + return MCTRCTL_M_ENABLE; + case PRV_S: + if (virt) { + return VSCTRCTL_VS_ENABLE; + } + return MCTRCTL_S_ENABLE; + case PRV_U: + if (virt) { + return VSCTRCTL_VU_ENABLE; + } + return MCTRCTL_U_ENABLE; + } + + g_assert_not_reached(); +} + +static uint64_t riscv_ctr_get_control(CPURISCVState *env, target_long priv, + bool virt) +{ + switch (priv) { + case PRV_M: + return env->mctrctl; + case PRV_S: + case PRV_U: + if (virt) { + return env->vsctrctl; + } + return env->mctrctl; + } + + g_assert_not_reached(); +} + +/* + * Special cases for traps and trap returns: + * + * 1- Traps, and trap returns, between enabled modes are recorded as norma= l. + * 2- Traps from an inhibited mode to an enabled mode, and trap returns fr= om an + * enabled mode back to an inhibited mode, are partially recorded. In such + * cases, the PC from the inhibited mode (source PC for traps, and target = PC + * for trap returns) is 0. + * + * 3- Trap returns from an inhibited mode to an enabled mode are not recor= ded. + * Traps from an enabled mode to an inhibited mode, known as external trap= s, + * receive special handling. + * By default external traps are not recorded, but a handshake mechanism e= xists + * to allow partial recording. Software running in the target mode of the= trap + * can opt-in to allowing CTR to record traps into that mode even when the= mode + * is inhibited. The MTE, STE, and VSTE bits allow M-mode, S-mode, and VS= -mode, + * respectively, to opt-in. When an External Trap occurs, and xTE=3D1, suc= h that + * x is the target privilege mode of the trap, will CTR record the trap. I= n such + * cases, the target PC is 0. + */ +/* + * CTR arrays are implemented as circular buffers and new entry is stored = at + * sctrstatus.WRPTR, but they are presented to software as moving circular + * buffers. Which means, software get's the illusion that whenever a new e= ntry + * is added the whole buffer is moved by one place and the new entry is ad= ded at + * the start keeping new entry at idx 0 and older ones follow. + * + * Depth =3D 16. + * + * buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F] + * WRPTR W + * entry 7 6 5 4 3 2 1 0 F E D C B A 9 8 + * + * When a new entry is added: + * buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F] + * WRPTR W + * entry 8 7 6 5 4 3 2 1 0 F E D C B A 9 + * + * entry here denotes the logical entry number that software can access + * using ctrsource, ctrtarget and ctrdata registers. So xiselect 0x200 + * will return entry 0 i-e buffer[8] and 0x201 will return entry 1 i-e + * buffer[7]. Here is how we convert entry to buffer idx. + * + * entry =3D isel - CTR_ENTRIES_FIRST; + * idx =3D (sctrstatus.WRPTR - entry - 1) & (depth - 1); + */ +void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, + uint64_t type, target_ulong src_priv, bool src_vi= rt) +{ + bool tgt_virt =3D env->virt_enabled; + uint64_t src_mask =3D riscv_ctr_priv_to_mask(src_priv, src_virt); + uint64_t tgt_mask =3D riscv_ctr_priv_to_mask(env->priv, tgt_virt); + uint64_t src_ctrl =3D riscv_ctr_get_control(env, src_priv, src_virt); + uint64_t tgt_ctrl =3D riscv_ctr_get_control(env, env->priv, tgt_virt); + uint64_t depth, head; + bool ext_trap =3D false; + + if (env->sctrstatus & SCTRSTATUS_FROZEN) { + return; + } + + /* + * With RAS Emul enabled, only allow Indirect, drirect calls, Function + * returns and Co-routine swap types. + */ + if (env->mctrctl & MCTRCTL_RASEMU && + type !=3D CTRDATA_TYPE_INDIRECT_CALL && + type !=3D CTRDATA_TYPE_DIRECT_CALL && + type !=3D CTRDATA_TYPE_RETURN && + type !=3D CTRDATA_TYPE_CO_ROUTINE_SWAP) { + return; + } + + if (type =3D=3D CTRDATA_TYPE_EXCEPTION || type =3D=3D CTRDATA_TYPE_INT= ERRUPT) { + /* Case 2 for traps. */ + if (!(src_ctrl & src_mask) && (tgt_ctrl & tgt_mask)) { + src =3D 0; + } else if ((src_ctrl & src_mask) && !(tgt_ctrl & tgt_mask)) { + /* Check if target priv-mode has allowed external trap recordi= ng. */ + if ((env->priv =3D=3D PRV_M && !(tgt_ctrl & MCTRCTL_MTE)) || + (env->priv =3D=3D PRV_S && !(tgt_ctrl & MCTRCTL_STE))) { + return; + } + + ext_trap =3D true; + dst =3D 0; + } else if (!(src_ctrl & src_mask) && !(tgt_ctrl & tgt_mask)) { + return; + } + } else if (type =3D=3D CTRDATA_TYPE_EXCEP_INT_RET) { + /* + * Case 3 for trap returns. Trap returns from inhibited mode are = not + * recorded. + */ + if (!(src_ctrl & src_mask)) { + return; + } + + /* Case 2 for trap returns. */ + if (!(tgt_ctrl & tgt_mask)) { + dst =3D 0; + } + } else if (!(tgt_ctrl & tgt_mask)) { + return; + } + + /* Ignore filters in case of RASEMU mode or External trap. */ + if (!(tgt_ctrl & MCTRCTL_RASEMU) && !ext_trap) { + /* + * Check if the specific type is inhibited. Not taken branch filte= r is + * an enable bit and needs to be checked separatly. + */ + bool check =3D tgt_ctrl & BIT_ULL(type + MCTRCTL_INH_START); + if ((type =3D=3D CTRDATA_TYPE_NONTAKEN_BRANCH && !check) || + (type !=3D CTRDATA_TYPE_NONTAKEN_BRANCH && check)) { + return; + } + } + + head =3D get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK); + + depth =3D 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); + if (tgt_ctrl & MCTRCTL_RASEMU && type =3D=3D CTRDATA_TYPE_RETURN) { + head =3D (head - 1) & (depth - 1); + + env->ctr_src[head] &=3D ~CTRSOURCE_VALID; + env->sctrstatus =3D + set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, head); + return; + } + + /* In case of Co-routine SWAP we overwrite latest entry. */ + if (tgt_ctrl & MCTRCTL_RASEMU && type =3D=3D CTRDATA_TYPE_CO_ROUTINE_S= WAP) { + head =3D (head - 1) & (depth - 1); + } + + env->ctr_src[head] =3D src | CTRSOURCE_VALID; + env->ctr_dst[head] =3D dst & ~CTRTARGET_MISP; + env->ctr_data[head] =3D set_field(0, CTRDATA_TYPE_MASK, type); + + head =3D (head + 1) & (depth - 1); + + env->sctrstatus =3D set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, = head); +} + void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool vir= t_en) { g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); @@ -1669,10 +1864,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1 << cause)); bool vs_injected =3D env->hvip & (1 << cause) & env->hvien && !(env->mip & (1 << cause)); + const bool prev_virt =3D env->virt_enabled; + const target_ulong prev_priv =3D env->priv; target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; + target_ulong src; =20 if (!async) { /* set tval to badaddr for traps with address information */ @@ -1729,6 +1927,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) tval =3D cs->watchpoint_hit->hitaddr; cs->watchpoint_hit =3D NULL; } + riscv_ctr_freeze(env, MCTRCTL_BPFRZ); break; default: break; @@ -1807,6 +2006,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S, virt); + + src =3D env->sepc; } else { /* handle the trap in M-mode */ if (riscv_has_ext(env, RVH)) { @@ -1838,8 +2039,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->pc =3D (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M, virt); + src =3D env->mepc; } =20 + riscv_ctr_add_entry(env, src, env->pc, + async ? CTRDATA_TYPE_INTERRUPT : CTRDATA_TYPE_EXCE= PTION, + prev_priv, prev_virt); + /* * NOTE: it is not necessary to yield load reservations here. It is on= ly * necessary for an SC from "another hart" to cause a load reservation diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 451261ce5a..0a9a545d87 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -129,12 +129,16 @@ DEF_HELPER_2(csrr_i128, tl, env, int) DEF_HELPER_4(csrw_i128, void, env, int, tl, tl) DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY -DEF_HELPER_1(sret, tl, env) -DEF_HELPER_1(mret, tl, env) +DEF_HELPER_2(sret, tl, env, tl) +DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(ctr_clear, void, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush_all, void, env) +DEF_HELPER_4(ctr_branch, void, env, tl, tl, tl) +DEF_HELPER_4(ctr_jal, void, env, tl, tl, tl) +DEF_HELPER_5(ctr_jalr, void, env, tl, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) #endif diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 4eccdddeaa..339d659151 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -78,9 +78,10 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); decode_save_opc(ctx); translator_io_start(&ctx->base); - gen_helper_sret(cpu_pc, tcg_env); + gen_helper_sret(cpu_pc, tcg_env, src); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; } else { @@ -95,9 +96,10 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); decode_save_opc(ctx); translator_io_start(&ctx->base); - gen_helper_mret(cpu_pc, tcg_env); + gen_helper_mret(cpu_pc, tcg_env, src); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; return true; diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index ad40d3e87f..7f95362b66 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -55,6 +55,11 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) TCGLabel *misaligned =3D NULL; TCGv target_pc =3D tcg_temp_new(); TCGv succ_pc =3D dest_gpr(ctx, a->rd); +#ifndef CONFIG_USER_ONLY + TCGv rd =3D tcg_constant_tl(a->rd); + TCGv rs1 =3D tcg_constant_tl(a->rs1); + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); +#endif =20 tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm); tcg_gen_andi_tl(target_pc, target_pc, (target_ulong)-2); @@ -75,6 +80,9 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) gen_set_gpr(ctx, a->rd, succ_pc); =20 tcg_gen_mov_tl(cpu_pc, target_pc); +#ifndef CONFIG_USER_ONLY + gen_helper_ctr_jalr(tcg_env, src, cpu_pc, rd, rs1); +#endif lookup_and_goto_ptr(ctx); =20 if (misaligned) { @@ -164,6 +172,11 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TC= GCond cond) TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_SIGN); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_SIGN); target_ulong orig_pc_save =3D ctx->pc_save; +#ifndef CONFIG_USER_ONLY + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); + TCGv taken; + TCGv dest; +#endif =20 if (get_xl(ctx) =3D=3D MXL_RV128) { TCGv src1h =3D get_gprh(ctx, a->rs1); @@ -176,6 +189,14 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TC= GCond cond) } else { tcg_gen_brcond_tl(cond, src1, src2, l); } + +#ifndef CONFIG_USER_ONLY + dest =3D tcg_constant_tl(ctx->base.pc_next + ctx->cur_insn_len); + taken =3D tcg_constant_tl(0); + + gen_helper_ctr_branch(tcg_env, src, dest, taken); +#endif + gen_goto_tb(ctx, 1, ctx->cur_insn_len); ctx->pc_save =3D orig_pc_save; =20 @@ -188,6 +209,12 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TC= GCond cond) gen_pc_plus_diff(target_pc, ctx, a->imm); gen_exception_inst_addr_mis(ctx, target_pc); } else { +#ifndef CONFIG_USER_ONLY + dest =3D tcg_constant_tl(ctx->base.pc_next + a->imm); + taken =3D tcg_constant_tl(1); + + gen_helper_ctr_branch(tcg_env, src, dest, taken); +#endif gen_goto_tb(ctx, 0, a->imm); } ctx->pc_save =3D -1; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 25a5263573..c8053d9c2f 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -259,10 +259,12 @@ void helper_cbo_inval(CPURISCVState *env, target_ulon= g address) =20 #ifndef CONFIG_USER_ONLY =20 -target_ulong helper_sret(CPURISCVState *env) +target_ulong helper_sret(CPURISCVState *env, target_ulong curr_pc) { uint64_t mstatus; target_ulong prev_priv, prev_virt =3D env->virt_enabled; + const target_ulong src_priv =3D env->priv; + const bool src_virt =3D env->virt_enabled; =20 if (!(env->priv >=3D PRV_S)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); @@ -309,11 +311,17 @@ target_ulong helper_sret(CPURISCVState *env) =20 riscv_cpu_set_mode(env, prev_priv, prev_virt); =20 + riscv_ctr_add_entry(env, curr_pc, retpc, CTRDATA_TYPE_EXCEP_INT_RET, + src_priv, src_virt); + return retpc; } =20 -target_ulong helper_mret(CPURISCVState *env) +target_ulong helper_mret(CPURISCVState *env, target_ulong curr_pc) { + const target_ulong src_priv =3D env->priv; + const bool src_virt =3D env->virt_enabled; + if (!(env->priv >=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } @@ -350,9 +358,109 @@ target_ulong helper_mret(CPURISCVState *env) =20 riscv_cpu_set_mode(env, prev_priv, prev_virt); =20 + riscv_ctr_add_entry(env, curr_pc, retpc, CTRDATA_TYPE_EXCEP_INT_RET, + src_priv, src_virt); + return retpc; } =20 +/* + * Indirect calls + * =E2=80=93 jalr x1, rs where rs !=3D x5; + * =E2=80=93 jalr x5, rs where rs !=3D x1; + * =E2=80=93 c.jalr rs1 where rs1 !=3D x5; + * + * Indirect jumps + * =E2=80=93 jalr x0, rs where rs !=3D x1 and rs !=3D x5; + * =E2=80=93 c.jr rs1 where rs1 !=3D x1 and rs1 !=3D x5. + * + * Returns + * =E2=80=93 jalr rd, rs where (rs =3D=3D x1 or rs =3D=3D x5) and rd !=3D = x1 and rd !=3D x5; + * =E2=80=93 c.jr rs1 where rs1 =3D=3D x1 or rs1 =3D=3D x5. + * + * Co-routine swap + * =E2=80=93 jalr x1, x5; + * =E2=80=93 jalr x5, x1; + * =E2=80=93 c.jalr x5. + * + * Other indirect jumps + * =E2=80=93 jalr rd, rs where rs !=3D x1, rs !=3D x5, rd !=3D x0, rd !=3D= x1 and rd !=3D x5. + */ +void helper_ctr_jalr(CPURISCVState *env, target_ulong src, target_ulong de= st, + target_ulong rd, target_ulong rs1) +{ + target_ulong curr_priv =3D env->priv; + bool curr_virt =3D env->virt_enabled; + + if ((rd =3D=3D 1 && rs1 !=3D 5) || (rd =3D=3D 5 && rs1 !=3D 1)) { + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_INDIRECT_CALL, + curr_priv, curr_virt); + } else if (rd =3D=3D 0 && rs1 !=3D 1 && rs1 !=3D 5) { + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_INDIRECT_JUMP, + curr_priv, curr_virt); + } else if ((rs1 =3D=3D 1 || rs1 =3D=3D 5) && (rd !=3D 1 && rd !=3D 5))= { + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_RETURN, + curr_priv, curr_virt); + } else if ((rs1 =3D=3D 1 && rd =3D=3D 5) || (rs1 =3D=3D 5 && rd =3D=3D= 1)) { + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_CO_ROUTINE_SWAP, + curr_priv, curr_virt); + } else { + riscv_ctr_add_entry(env, src, dest, + CTRDATA_TYPE_OTHER_INDIRECT_JUMP, curr_priv, + curr_virt); + } +} + +/* + * Direct calls + * =E2=80=93 jal x1; + * =E2=80=93 jal x5; + * =E2=80=93 c.jal. + * + * Direct jumps + * =E2=80=93 jal x0; + * =E2=80=93 c.j; + * + * Other direct jumps + * =E2=80=93 jal rd where rd !=3D x1 and rd !=3D x5 and rd !=3D x0; + */ +void helper_ctr_jal(CPURISCVState *env, target_ulong src, target_ulong des= t, + target_ulong rd) +{ + target_ulong priv =3D env->priv; + bool virt =3D env->virt_enabled; + + /* + * If rd is x1 or x5 link registers, treat this as direct call otherwi= se + * its a direct jump. + */ + if (rd =3D=3D 1 || rd =3D=3D 5) { + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_DIRECT_CALL, priv, + virt); + } else if (rd =3D=3D 0) { + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_DIRECT_JUMP, priv, + virt); + } else { + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_OTHER_DIRECT_JUMP, + priv, virt); + } +} + +void helper_ctr_branch(CPURISCVState *env, target_ulong src, target_ulong = dest, + target_ulong branch_taken) +{ + target_ulong curr_priv =3D env->priv; + bool curr_virt =3D env->virt_enabled; + + if (branch_taken) { + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_TAKEN_BRANCH, + curr_priv, curr_virt); + } else { + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_NONTAKEN_BRANCH, + curr_priv, curr_virt); + } +} + void helper_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 15e7123a68..8b0492991d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -561,6 +561,11 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_n= um, TCGv_i64 t) static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { TCGv succ_pc =3D dest_gpr(ctx, rd); +#ifndef CONFIG_USER_ONLY + TCGv dest =3D tcg_constant_tl(ctx->base.pc_next + imm); + TCGv src =3D tcg_constant_tl(ctx->base.pc_next); + TCGv tcg_rd =3D tcg_constant_tl((target_ulong)rd); +#endif =20 /* check misaligned: */ if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { @@ -572,6 +577,10 @@ static void gen_jal(DisasContext *ctx, int rd, target_= ulong imm) } } =20 +#ifndef CONFIG_USER_ONLY + gen_helper_ctr_jal(tcg_env, src, dest, tcg_rd); +#endif + gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); gen_set_gpr(ctx, rd, succ_pc); =20 --=20 2.34.1