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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716905565324100007 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20240524232121.284515-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 11 ++++ target/arm/tcg/translate-a64.c | 97 ++++++++-------------------------- 2 files changed, 32 insertions(+), 76 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 350afabc779..c342c276089 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -31,6 +31,7 @@ @rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=3D1 esz= =3D0 @r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=3D%rd q= =3D1 esz=3D0 @rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=3D1 esz= =3D0 +@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=3D1 esz= =3D3 =20 ### Data Processing - Immediate =20 @@ -620,3 +621,13 @@ SHA256SU1 0101 1110 000 ..... 011000 ..... .....= @rrr_q1e0 SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 + +### Cryptographic three-register SHA512 + +SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 +SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 +SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 +RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 +SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 +SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 +SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1d20bf0c35b..77b24cd52ed 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1341,6 +1341,17 @@ static bool do_gvec_op3_ool(DisasContext *s, arg_qrr= r_e *a, int data, return true; } =20 +static bool do_gvec_fn3(DisasContext *s, arg_qrrr_e *a, GVecGen3Fn *fn) +{ + if (!a->q && a->esz =3D=3D MO_64) { + return false; + } + if (fp_access_check(s)) { + gen_gvec_fn3(s, a->q, a->rd, a->rn, a->rm, fn, a->esz); + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the @@ -4589,7 +4600,7 @@ static bool trans_EXTR(DisasContext *s, arg_extract *= a) } =20 /* - * Cryptographic AES, SHA + * Cryptographic AES, SHA, SHA512 */ =20 TRANS_FEAT(AESE, aa64_aes, do_gvec_op3_ool, a, 0, gen_helper_crypto_aese) @@ -4610,6 +4621,15 @@ TRANS_FEAT(SHA1H, aa64_sha1, do_gvec_op2_ool, a, 0, = gen_helper_crypto_sha1h) TRANS_FEAT(SHA1SU1, aa64_sha1, do_gvec_op2_ool, a, 0, gen_helper_crypto_sh= a1su1) TRANS_FEAT(SHA256SU0, aa64_sha256, do_gvec_op2_ool, a, 0, gen_helper_crypt= o_sha256su0) =20 +TRANS_FEAT(SHA512H, aa64_sha512, do_gvec_op3_ool, a, 0, gen_helper_crypto_= sha512h) +TRANS_FEAT(SHA512H2, aa64_sha512, do_gvec_op3_ool, a, 0, gen_helper_crypto= _sha512h2) +TRANS_FEAT(SHA512SU1, aa64_sha512, do_gvec_op3_ool, a, 0, gen_helper_crypt= o_sha512su1) +TRANS_FEAT(RAX1, aa64_sha3, do_gvec_fn3, a, gen_gvec_rax1) +TRANS_FEAT(SM3PARTW1, aa64_sm3, do_gvec_op3_ool, a, 0, gen_helper_crypto_s= m3partw1) +TRANS_FEAT(SM3PARTW2, aa64_sm3, do_gvec_op3_ool, a, 0, gen_helper_crypto_s= m3partw2) +TRANS_FEAT(SM4EKEY, aa64_sm4, do_gvec_op3_ool, a, 0, gen_helper_crypto_sm4= ekey) + + /* Shift a TCGv src by TCGv shift_amount, put result in dst. * Note that it is the caller's responsibility to ensure that the * shift amount is in range (ie 0..31 or 0..63) and provide the ARM @@ -13510,80 +13530,6 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) } } =20 -/* Crypto three-reg SHA512 - * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 - * +-----------------------+------+---+---+-----+--------+------+------+ - * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd | - * +-----------------------+------+---+---+-----+--------+------+------+ - */ -static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) -{ - int opcode =3D extract32(insn, 10, 2); - int o =3D extract32(insn, 14, 1); - int rm =3D extract32(insn, 16, 5); - int rn =3D extract32(insn, 5, 5); - int rd =3D extract32(insn, 0, 5); - bool feature; - gen_helper_gvec_3 *oolfn =3D NULL; - GVecGen3Fn *gvecfn =3D NULL; - - if (o =3D=3D 0) { - switch (opcode) { - case 0: /* SHA512H */ - feature =3D dc_isar_feature(aa64_sha512, s); - oolfn =3D gen_helper_crypto_sha512h; - break; - case 1: /* SHA512H2 */ - feature =3D dc_isar_feature(aa64_sha512, s); - oolfn =3D gen_helper_crypto_sha512h2; - break; - case 2: /* SHA512SU1 */ - feature =3D dc_isar_feature(aa64_sha512, s); - oolfn =3D gen_helper_crypto_sha512su1; - break; - case 3: /* RAX1 */ - feature =3D dc_isar_feature(aa64_sha3, s); - gvecfn =3D gen_gvec_rax1; - break; - default: - g_assert_not_reached(); - } - } else { - switch (opcode) { - case 0: /* SM3PARTW1 */ - feature =3D dc_isar_feature(aa64_sm3, s); - oolfn =3D gen_helper_crypto_sm3partw1; - break; - case 1: /* SM3PARTW2 */ - feature =3D dc_isar_feature(aa64_sm3, s); - oolfn =3D gen_helper_crypto_sm3partw2; - break; - case 2: /* SM4EKEY */ - feature =3D dc_isar_feature(aa64_sm4, s); - oolfn =3D gen_helper_crypto_sm4ekey; - break; - default: - unallocated_encoding(s); - return; - } - } - - if (!feature) { - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - - if (oolfn) { - gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn); - } else { - gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64); - } -} - /* Crypto two-reg SHA512 * 31 12 11 10 9 5 4 0 * +-----------------------------------------+--------+------+------+ @@ -13804,7 +13750,6 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, - { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 }, { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 }, { 0xce000000, 0xff808000, disas_crypto_four_reg }, { 0xce800000, 0xffe00000, disas_crypto_xar }, --=20 2.34.1