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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/42] target/arm: Zero-extend writeback for fp16 FCVTZS
(scalar, integer)
Date: Tue, 28 May 2024 15:07:21 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Fixes RISU mismatch for "fcvtzs h31, h0, #14".
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate-a64.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 4126aaa27e6..d97acdbaf9a 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8707,6 +8707,9 @@ static void handle_simd_shift_fpint_conv(DisasContext=
*s, bool is_scalar,
read_vec_element_i32(s, tcg_op, rn, pass, size);
fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
if (is_scalar) {
+ if (size =3D=3D MO_16 && !is_u) {
+ tcg_gen_ext16u_i32(tcg_op, tcg_op);
+ }
write_fp_sreg(s, rd, tcg_op);
} else {
write_vec_element_i32(s, tcg_op, rd, pass, size);
--=20
2.34.1