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[114.34.225.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c9a4fadsm79481175ad.224.2024.05.28.06.04.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 28 May 2024 06:04:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1716901476; x=1717506276; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TkWDWLJe6ifCLfRxbVy6kaBipu+b3OffSbkRgfkqXg0=; b=VrR84w7i8k+eYVQKKiHyrea14CvMvKWYfSgu/tniICbgA+S8+nZ6g/iaBzOLyhKGfN 5WrRuM9UqKxScQWvoJQSb36qlhcU3/4AypU3mkDoujztkA1jHSbWr31LeHLnHgCvrY6g sZAXnJJmD6d/u0BBLhlx6X90nyZy1zvVOnxrTEUmuau37UsPyZczwcnnTOm2V8XVb1NN ubs4nDwnt285o3+B7bUyj7Pcl3ISQ4o8PO3XbVbkzQEKCAx1RrqoTZ0jO029vEVakkcl 17CDC41iRCRk6X5WJpHuWEBTYqzs0eY7Ufg6onogGdrg0Uzf8o5qCyB3oI4xqcrrfVWJ 9WBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716901476; x=1717506276; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TkWDWLJe6ifCLfRxbVy6kaBipu+b3OffSbkRgfkqXg0=; b=Cxz8rIUVpMmUc8D6dnXcj97bDxVmgxrEe/mKyi/8pH+RAO8WPEs6vA3/MV1ou/owX3 IkRy1A96KHXuVZGjTTo2khg3pC3jghBgKIxlxftPHDPMmkx5bQj/3jsinfCj7/uK/WMM 0Pln2B2LvBc7D2EE85i8oi/BYz4Qjsd+Q8PkItvMubGrCiX6nnXG7KpR83fDDa0yVCqP H8OVgsh4d5M7VE8ZmJnlWYxtP3Oo8lK+U4Thw/8GRG3Puw0oAA6J8A40d70P/6n+mAwc zCZ+n3ELD0wb19ZCjL3b+ldDatwczByV0gd1lELZIQ2nmdbavvw7T1dfr4mumDb1WVh1 oEEw== X-Forwarded-Encrypted: i=1; AJvYcCXrDModa/9tXzcBnZ0YhMMHmrEFDCNGs3jpZcEbVa4S420B9tl+Enu3eyXPMfah444nMmrpH167n+0QvT6hCLjjeSjlk10= X-Gm-Message-State: AOJu0YyhXToh0HajnKOoIq7eb3uHM3K/GFgIX9XnG7gr5BApTARXZCsB pq6h90Ix9nScWzJRcfI2u6WaAp99cSTZBrr+0PN+fB/pxQeENQmsm8nD5if0n5c= X-Google-Smtp-Source: AGHT+IFaCmHXurXlxjQhMH+5Sl1ud38kk4HTNfVgoY+HDisd5J7h/p6LyFY8jCzoNwR+aPzn7hN1Sg== X-Received: by 2002:a17:903:192:b0:1f4:5477:4bf2 with SMTP id d9443c01a7336-1f454774e12mr128639375ad.42.1716901476194; Tue, 28 May 2024 06:04:36 -0700 (PDT) From: Jerry Zhang Jian To: alistair.francis@wdc.com, palmer@dabbelt.com, frank.chang@sifive.com, max.chou@sifive.com, paul.walmsley@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jerry Zhang Jian Subject: [PATCH v2] target/riscv: zvbb implies zvkb Date: Tue, 28 May 2024 21:03:49 +0800 Message-ID: <20240528130349.20193-1-jerry.zhangjian@sifive.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240516123336.63534-1-jerry.zhangjian@sifive.com> References: <20240516123336.63534-1-jerry.zhangjian@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=jerry.zhangjian@sifive.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1716901542451100001 Content-Type: text/plain; charset="utf-8" - According to RISC-V crypto spec, Zvkb extension is a proper subset of the= Zvbb extension. - Reference: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e= 0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=3D1#L10 Signed-off-by: Jerry Zhang Jian --- target/riscv/tcg/tcg-cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 40054a391a..f1a1306ab2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); } =20 + if (cpu->cfg.ext_zvbb) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); + } + /* * In principle Zve*x would also suffice here, were they supported * in qemu --=20 2.44.0