From nobody Mon Nov 25 17:54:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=reject dis=none) header.from=linux.ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17168800298609.28040933238617; Tue, 28 May 2024 00:07:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBquz-0007Kq-Lk; Tue, 28 May 2024 03:06:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBqun-0007AO-B3; Tue, 28 May 2024 03:06:33 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBquc-0004kj-92; Tue, 28 May 2024 03:06:28 -0400 Received: from pps.filterd (m0353723.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 44S6F5Ts016212; Tue, 28 May 2024 07:05:37 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3yd88ugbdu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 May 2024 07:05:37 +0000 Received: from m0353723.ppops.net (m0353723.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 44S75axC031801; Tue, 28 May 2024 07:05:36 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3yd88ugbdt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 May 2024 07:05:36 +0000 Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 44S6Z2cD032263; Tue, 28 May 2024 07:05:36 GMT Received: from smtprelay01.fra02v.mail.ibm.com ([9.218.2.227]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3ybutm595k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 May 2024 07:05:35 +0000 Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44S75Uke56295918 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 28 May 2024 07:05:32 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4C1E32004D; Tue, 28 May 2024 07:05:30 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6A79720040; Tue, 28 May 2024 07:05:28 +0000 (GMT) Received: from li-3c92a0cc-27cf-11b2-a85c-b804d9ca68fa.in.ibm.com (unknown [9.109.199.72]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 28 May 2024 07:05:28 +0000 (GMT) DKIM-Signature: =?UTF-8?Q?v=3D1; _a=3Drsa-sha256; _c=3Drelaxed/relaxed; _d=3Dibm.com; _h=3Dcc?= =?UTF-8?Q?:content-transfer-encoding:content-type:date:from:in-reply-to:m?= =?UTF-8?Q?essage-id:mime-version:references:subject:to;_s=3Dpp1;_bh=3D21G?= =?UTF-8?Q?exMEuHbB5omvU65qI+tUd5tA6bzrb16XAIpgIbZg=3D;_b=3DL9fTMwLEiplcHK?= =?UTF-8?Q?TkU66LoJ2bkIbU6Eb63qpQle2u+2rzxTVbdorlUF3BWb286GDC2LGu_IkJZlLl4?= =?UTF-8?Q?jqXQ78U5pukP4KMfuPapXhBB28cjoR0YUiyGENj/5MiObYZKcOy5XTIGPott_3g?= =?UTF-8?Q?+Wm5CaOJKLQsAIXUKp60XHgXuvElGZkGEYuLMIgZjvYzQ8EouuIwqJn90tEQJh6?= =?UTF-8?Q?Mfz_O6oS+E6HcJLpdxebJPEvSwhw84qDrUhu5Ncgb/ZKXLFZYKoc3yWpgH2wxK6?= =?UTF-8?Q?X1b69xDec_gv2VG8TrbTpuU6+UA2cyDqk109Q2k7vSdGD8vXqAhOTm/rCcCU2th?= =?UTF-8?Q?RHeQCBv7U+X5sBJ_AQ=3D=3D_?= From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Cc: , , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH v4 05/11] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine Date: Tue, 28 May 2024 12:35:09 +0530 Message-ID: <20240528070515.117160-6-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528070515.117160-1-adityag@linux.ibm.com> References: <20240528070515.117160-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: abxAIZQ2hlE-dTKdrL2Bvm-kGHNg8cBK X-Proofpoint-ORIG-GUID: CYAJG7aiJVcliACHMtX_GxTG-rTvcqbS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-28_04,2024-05-27_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 mlxscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716880031154100002 Power11 core is same as Power10, use the existing functionalities to introduce a Power11 chip and machine, with Power10 chip as parent of Power11 chip, thus going through similar class_init paths Cc: C=C3=A9dric Le Goater Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Signed-off-by: Aditya Gupta --- docs/system/ppc/powernv.rst | 9 +-- hw/ppc/pnv.c | 120 ++++++++++++++++++++++++++++++++++-- hw/ppc/pnv_core.c | 11 ++++ include/hw/ppc/pnv.h | 5 ++ include/hw/ppc/pnv_chip.h | 7 +++ include/hw/ppc/pnv_core.h | 1 + 6 files changed, 145 insertions(+), 8 deletions(-) diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst index 09f39658587d..65606aa767aa 100644 --- a/docs/system/ppc/powernv.rst +++ b/docs/system/ppc/powernv.rst @@ -1,5 +1,5 @@ -PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powern= v11``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 PowerNV (as Non-Virtualized) is the "bare metal" platform using the OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can @@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today. Supported devices ----------------- =20 - * Multi processor support for POWER8, POWER8NVL and POWER9. + * Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Powe= r11. * XSCOM, serial communication sideband bus to configure chiplets. * Simple LPC Controller. * Processor Service Interface (PSI) Controller. - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power1= 0). + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power1= 0 & + Power11). * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge. * Simple OCC is an on-chip micro-controller used for power management tas= ks. * iBT device to handle BMC communication, with the internal BMC simulator diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 6e3a5ccdec76..f8270f4b123b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -456,6 +456,33 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip= , void *fdt) pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); } =20 +static void pnv_chip_power11_dt_populate(PnvChip *chip, void *fdt) +{ + static const char compat[] =3D "ibm,power11-xscom\0ibm,xscom"; + int i; + + pnv_dt_xscom(chip, fdt, 0, + cpu_to_be64(PNV10_XSCOM_BASE(chip)), + cpu_to_be64(PNV10_XSCOM_SIZE), + compat, sizeof(compat)); + + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pnv_core =3D chip->cores[i]; + int offset; + + offset =3D pnv_dt_core(chip, pnv_core, fdt); + + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", + pa_features_31, sizeof(pa_features_31)))); + } + + if (chip->ram_size) { + pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); + } + + pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); +} + static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) { uint32_t io_base =3D d->ioport_id; @@ -1288,6 +1315,8 @@ static void pnv_chip_power10_intc_print_info(PnvChip = *chip, PowerPCCPU *cpu, =20 #define POWER10_CORE_MASK (0xffffffffffffffull) =20 +#define POWER11_CORE_MASK (0xffffffffffffffull) + static void pnv_chip_power8_instance_init(Object *obj) { Pnv8Chip *chip8 =3D PNV8_CHIP(obj); @@ -1831,7 +1860,8 @@ static void pnv_chip_power10_instance_init(Object *ob= j) } } =20 -static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) +static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp, + const char *cpu_model) { PnvChip *chip =3D PNV_CHIP(chip10); int i; @@ -1841,9 +1871,10 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip = *chip10, Error **errp) =20 for (i =3D 0; i < chip10->nr_quads; i++) { PnvQuad *eq =3D &chip10->quads[i]; + g_autofree char *type_name =3D PNV_QUAD_TYPE_NAME_DYN(cpu_model); =20 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], - PNV_QUAD_TYPE_NAME("power10")); + type_name); =20 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), &eq->xscom_regs); @@ -1881,7 +1912,8 @@ static void pnv_chip_power10_phb_realize(PnvChip *chi= p, Error **errp) } } =20 -static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) +static void pnv_chip_power10_common_realize(DeviceState *dev, Error **errp, + const char *cpu_model) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); PnvChip *chip =3D PNV_CHIP(dev); @@ -1898,7 +1930,7 @@ static void pnv_chip_power10_realize(DeviceState *dev= , Error **errp) return; } =20 - pnv_chip_power10_quad_realize(chip10, &local_err); + pnv_chip_power10_quad_realize(chip10, &local_err, cpu_model); if (local_err) { error_propagate(errp, local_err); return; @@ -2046,6 +2078,16 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) =20 } =20 +static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) +{ + pnv_chip_power10_common_realize(dev, errp, "power10"); +} + +static void pnv_chip_power11_realize(DeviceState *dev, Error **errp) +{ + pnv_chip_power10_common_realize(dev, errp, "power11"); +} + static void pnv_rainier_i2c_init(PnvMachineState *pnv) { int i; @@ -2111,6 +2153,34 @@ static void pnv_chip_power10_class_init(ObjectClass = *klass, void *data) &k->parent_realize); } =20 +static void pnv_chip_power11_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvChipClass *k =3D PNV_CHIP_CLASS(klass); + + static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] =3D {14, 14,= 2, 16}; + + k->chip_cfam_id =3D 0x220da04980000000ull; /* P11 DD2.0 (with NX) */ + k->cores_mask =3D POWER11_CORE_MASK; + k->chip_pir =3D pnv_chip_pir_p10; + k->intc_create =3D pnv_chip_power10_intc_create; + k->intc_reset =3D pnv_chip_power10_intc_reset; + k->intc_destroy =3D pnv_chip_power10_intc_destroy; + k->intc_print_info =3D pnv_chip_power10_intc_print_info; + k->isa_create =3D pnv_chip_power10_isa_create; + k->dt_populate =3D pnv_chip_power11_dt_populate; + k->pic_print_info =3D pnv_chip_power10_pic_print_info; + k->xscom_core_base =3D pnv_chip_power10_xscom_core_base; + k->xscom_pcba =3D pnv_chip_power10_xscom_pcba; + dc->desc =3D "PowerNV Chip POWER11"; + k->num_pecs =3D PNV10_CHIP_MAX_PEC; + k->i2c_num_engines =3D PNV10_CHIP_MAX_I2C; + k->i2c_ports_per_engine =3D i2c_ports_per_engine; + + device_class_set_parent_realize(dc, pnv_chip_power11_realize, + &k->parent_realize); +} + static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); @@ -2505,6 +2575,22 @@ static void pnv_machine_p10_rainier_class_init(Objec= tClass *oc, void *data) pmc->i2c_init =3D pnv_rainier_i2c_init; } =20 +static void pnv_machine_power11_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); + static const char compat[] =3D "qemu,powernv11\0ibm,powernv"; + + /* do power10_class_init as p11 core is same as p10 */ + pnv_machine_p10_common_class_init(oc, data); + + mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER11"; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power11_v2.0"); + + pmc->compat =3D compat; + pmc->compat_size =3D sizeof(compat); +} + static bool pnv_machine_get_hb(Object *obj, Error **errp) { PnvMachineState *pnv =3D PNV_MACHINE(obj); @@ -2608,7 +2694,23 @@ static void pnv_machine_class_init(ObjectClass *oc, = void *data) .parent =3D TYPE_PNV10_CHIP, \ } =20 +#define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV11_CHIP, \ + } + static const TypeInfo types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("powernv11"), + .parent =3D TYPE_PNV_MACHINE, + .class_init =3D pnv_machine_power11_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_XIVE_FABRIC }, + { }, + }, + }, { .name =3D MACHINE_TYPE_NAME("powernv10-rainier"), .parent =3D MACHINE_TYPE_NAME("powernv10"), @@ -2663,6 +2765,16 @@ static const TypeInfo types[] =3D { .abstract =3D true, }, =20 + /* + * P11 chip and variants + */ + { + .name =3D TYPE_PNV11_CHIP, + .parent =3D TYPE_PNV10_CHIP, + .instance_size =3D sizeof(Pnv11Chip), + }, + DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_i= nit), + /* * P10 chip and variants */ diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index f40ab721d6fc..87c2e7ce2084 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -372,6 +372,11 @@ static void pnv_core_power10_class_init(ObjectClass *o= c, void *data) pcc->xscom_size =3D PNV10_XSCOM_EC_SIZE; } =20 +static void pnv_core_power11_class_init(ObjectClass *oc, void *data) +{ + pnv_core_power10_class_init(oc, data); +} + static void pnv_core_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -403,6 +408,7 @@ static const TypeInfo pnv_core_infos[] =3D { DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), + DEFINE_PNV_CORE_TYPE(power11, "power11_v2.0"), }; =20 DEFINE_TYPES(pnv_core_infos) @@ -634,6 +640,11 @@ static const TypeInfo pnv_quad_infos[] =3D { .name =3D PNV_QUAD_TYPE_NAME("power10"), .class_init =3D pnv_quad_power10_class_init, }, + { + .parent =3D PNV_QUAD_TYPE_NAME("power10"), + .name =3D PNV_QUAD_TYPE_NAME("power11"), + .class_init =3D pnv_quad_power10_class_init, + }, }; =20 DEFINE_TYPES(pnv_quad_infos); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 476b13614640..386aab0478d3 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -33,6 +33,7 @@ typedef struct PnvChip PnvChip; typedef struct Pnv8Chip Pnv8Chip; typedef struct Pnv9Chip Pnv9Chip; typedef struct Pnv10Chip Pnv10Chip; +typedef struct Pnv10Chip Pnv11Chip; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX @@ -57,6 +58,10 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, TYPE_PNV_CHIP_POWER10) =20 +#define TYPE_PNV_CHIP_POWER11 PNV_CHIP_TYPE_NAME("power11_v2.0") +DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER11, + TYPE_PNV_CHIP_POWER11) + PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id); PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); =20 diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 8589f3291ed3..3aefef051995 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -132,6 +132,13 @@ struct Pnv10Chip { #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) =20 +#define TYPE_PNV11_CHIP "pnv11-chip" +DECLARE_INSTANCE_CHECKER(Pnv11Chip, PNV11_CHIP, + TYPE_PNV11_CHIP) + +/* Power11 core is same as Power10 */ +typedef struct Pnv10Chip Pnv11Chip; + struct PnvChipClass { /*< private >*/ SysBusDeviceClass parent_class; diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index c6d62fd14593..9e9a305061d0 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -76,6 +76,7 @@ struct PnvQuadClass { =20 #define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD #define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX +#define PNV_QUAD_TYPE_NAME_DYN(cpu) g_strconcat(cpu, PNV_QUAD_TYPE_SUFFIX,= NULL) =20 OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD) =20 --=20 2.45.1