From nobody Mon Nov 25 16:30:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=reject dis=none) header.from=linux.ibm.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716880029751637.8086866479525; Tue, 28 May 2024 00:07:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBquo-0007AU-5K; Tue, 28 May 2024 03:06:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBqum-0007A1-4F; Tue, 28 May 2024 03:06:32 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBquK-0004jl-Nx; Tue, 28 May 2024 03:06:23 -0400 Received: from pps.filterd (m0360072.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 44S5grBZ005810; Tue, 28 May 2024 07:05:27 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3yd9bw0609-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 May 2024 07:05:27 +0000 Received: from m0360072.ppops.net (m0360072.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 44S75QM8001538; Tue, 28 May 2024 07:05:26 GMT Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3yd9bw0607-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 May 2024 07:05:26 +0000 Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 44S4wkgM006684; Tue, 28 May 2024 07:05:26 GMT Received: from smtprelay02.fra02v.mail.ibm.com ([9.218.2.226]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3ybtatdqf7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 May 2024 07:05:26 +0000 Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay02.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44S75KnV46989694 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 28 May 2024 07:05:23 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C998D2004B; Tue, 28 May 2024 07:05:20 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 815A220063; Tue, 28 May 2024 07:05:18 +0000 (GMT) Received: from li-3c92a0cc-27cf-11b2-a85c-b804d9ca68fa.in.ibm.com (unknown [9.109.199.72]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 28 May 2024 07:05:18 +0000 (GMT) DKIM-Signature: =?UTF-8?Q?v=3D1; _a=3Drsa-sha256; _c=3Drelaxed/relaxed; _d=3Dibm.com; _h=3Dcc?= =?UTF-8?Q?:content-transfer-encoding:content-type:date:from:in-reply-to:m?= =?UTF-8?Q?essage-id:mime-version:references:subject:to;_s=3Dpp1;_bh=3DX4l?= =?UTF-8?Q?lEPElQhoZtGfyFUPU7qCkUth7SOaEvYBtvtTgGYU=3D;_b=3DTD6mAVJ0kIl0DE?= =?UTF-8?Q?m6WrkFuRWKe2qJGv+JR18UioH9CPpeFOsydEUOsK69KUm7N89KKJBR_6+IwQdcJ?= =?UTF-8?Q?zi1c+XjaCkOICydSB/9GzUkezvHpO7h1Nxl0fuYt5KyoV2dHtrcj+CfFPqP+_gN?= =?UTF-8?Q?kbX3Pd2F0W7RJGl8JTm6yi7Psech0Hbbzhc+/Mrqe31EQ6XegovOCjMc8c+nyH7?= =?UTF-8?Q?CJ7_ieqOwguQiNNNQ1jhrQ20Kszk3PaER0436ZcGgnyJODeEKXLVKZdkDGC7Ppr?= =?UTF-8?Q?eE2NXfhmz_7rvQoUuL30wV0v3wUKoS7gK1lJSXOwiOWm6RYiPxp9vAdVR8KKlKd?= =?UTF-8?Q?JFtbDxT4hVMCKPp_wg=3D=3D_?= From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Cc: , , Daniel Henrique Barboza , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Subject: [PATCH v4 01/11] ppc: Add Power11 DD2.0 processor Date: Tue, 28 May 2024 12:35:05 +0530 Message-ID: <20240528070515.117160-2-adityag@linux.ibm.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528070515.117160-1-adityag@linux.ibm.com> References: <20240528070515.117160-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Dmkofaux9OjX863t1TKyysx3fIJhN-qG X-Proofpoint-ORIG-GUID: UlEqtz-nD9nZ4xWS7lkG1tYaVzNRPPvS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-28_04,2024-05-27_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1015 mlxscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405280050 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716880031127100001 Add CPU target code to add support for new Power11 Processor. Power11 core is same as Power10, hence reuse functions defined for Power10. Cc: C=C3=A9dric Le Goater Cc: Daniel Henrique Barboza Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Signed-off-by: Aditya Gupta --- target/ppc/compat.c | 7 +++ target/ppc/cpu-models.c | 3 ++ target/ppc/cpu-models.h | 3 ++ target/ppc/cpu_init.c | 102 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 115 insertions(+) diff --git a/target/ppc/compat.c b/target/ppc/compat.c index ebef2cccecf3..12dd8ae290ca 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] =3D { .pcr_level =3D PCR_COMPAT_3_10, .max_vthreads =3D 8, }, + { /* POWER11, ISA3.10 */ + .name =3D "power11", + .pvr =3D CPU_POWERPC_LOGICAL_3_10_PLUS, + .pcr =3D PCR_COMPAT_3_10, + .pcr_level =3D PCR_COMPAT_3_10, + .max_vthreads =3D 8, + }, }; =20 static const CompatInfo *compat_by_pvr(uint32_t pvr) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index f2301b43f78b..ece348178188 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -734,6 +734,8 @@ "POWER9 v2.2") POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER= 10, "POWER10 v2.0") + POWERPC_DEF("power11_v2.0", CPU_POWERPC_POWER11_DD20, POWER= 11, + "POWER11_v2.0") #endif /* defined (TARGET_PPC64) */ =20 /*************************************************************************= **/ @@ -909,6 +911,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] =3D { { "power8nvl", "power8nvl_v1.0" }, { "power9", "power9_v2.2" }, { "power10", "power10_v2.0" }, + { "power11", "power11_v2.0" }, #endif =20 /* Generic PowerPCs */ diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0229ef3a9a5c..ef74e387b047 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -354,6 +354,8 @@ enum { CPU_POWERPC_POWER10_BASE =3D 0x00800000, CPU_POWERPC_POWER10_DD1 =3D 0x00801100, CPU_POWERPC_POWER10_DD20 =3D 0x00801200, + CPU_POWERPC_POWER11_BASE =3D 0x00820000, + CPU_POWERPC_POWER11_DD20 =3D 0x00821200, CPU_POWERPC_970_v22 =3D 0x00390202, CPU_POWERPC_970FX_v10 =3D 0x00391100, CPU_POWERPC_970FX_v20 =3D 0x003C0200, @@ -391,6 +393,7 @@ enum { CPU_POWERPC_LOGICAL_2_07 =3D 0x0F000004, CPU_POWERPC_LOGICAL_3_00 =3D 0x0F000005, CPU_POWERPC_LOGICAL_3_10 =3D 0x0F000006, + CPU_POWERPC_LOGICAL_3_10_PLUS =3D 0x0F000007, }; =20 /* System version register (used on MPC 8xxx) = */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 01e358a4a5ac..82d700382cdd 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6763,6 +6763,108 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->l1_icache_size =3D 0x8000; } =20 +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool= best) +{ + uint32_t base =3D pvr & CPU_POWERPC_POWER_SERVER_MASK; + uint32_t pcc_base =3D pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; + + if (!best && (base =3D=3D CPU_POWERPC_POWER11_BASE)) { + return true; + } + + if (base !=3D pcc_base) { + return false; + } + + if ((pvr & 0x0f00) =3D=3D (pcc->pvr & 0x0f00)) { + return true; + } + + return false; +} + +POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->fw_name =3D "PowerPC,POWER11"; + dc->desc =3D "POWER11"; + pcc->pvr_match =3D ppc_pvr_match_power11; + pcc->pcr_mask =3D PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | + PCR_COMPAT_3_00; + pcc->pcr_supported =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_= 2_07 | + PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->init_proc =3D init_proc_POWER10; + pcc->check_pow =3D check_pow_nocheck; + pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; + pcc->msr_mask =3D (1ull << MSR_SF) | + (1ull << MSR_HV) | + (1ull << MSR_TM) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->lpcr_mask =3D LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | + LPCR_DEE | LPCR_OEE)) + | LPCR_MER | LPCR_GTSE | LPCR_TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + /* DD2 adds an extra HAIL bit */ + pcc->lpcr_mask |=3D LPCR_HAIL; + + pcc->lpcr_pm =3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OE= E; + pcc->mmu_model =3D POWERPC_MMU_3_00; +#if !defined(CONFIG_USER_ONLY) + /* segment page size remain the same */ + pcc->hash64_opts =3D &ppc_hash64_opts_POWER7; + pcc->radix_page_info =3D &POWER10_radix_page_info; + pcc->lrg_decr_bits =3D 56; +#endif + pcc->excp_model =3D POWERPC_EXCP_POWER10; + pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach =3D bfd_mach_ppc64; + pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; + pcc->l1_dcache_size =3D 0x8000; + pcc->l1_icache_size =3D 0x8000; +} + #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { --=20 2.45.1