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From: Alistair Francis <alistair23@gmail.com>
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=?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= <cleger@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception
number to 63
Date: Tue, 28 May 2024 12:43:06 +1000
Message-ID: <20240528024328.246965-7-alistair.francis@wdc.com>
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From: Cl=C3=A9ment L=C3=A9ger <cleger@rivosinc.com>
The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.
Signed-off-by: Cl=C3=A9ment L=C3=A9ger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fc2068ee4d..74318a925c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -670,11 +670,11 @@ typedef enum RISCVException {
RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */
RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */
RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */
- RISCV_EXCP_SEMIHOST =3D 0x10,
RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14,
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT =3D 0x15,
RISCV_EXCP_VIRT_INSTRUCTION_FAULT =3D 0x16,
RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT =3D 0x17,
+ RISCV_EXCP_SEMIHOST =3D 0x3f,
} RISCVException;
=20
#define RISCV_EXCP_INT_FLAG 0x80000000
--=20
2.45.1