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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Yu-Ming Chang <yumin686@andestech.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes
a read-only CSR
Date: Tue, 28 May 2024 12:43:28 +1000
Message-ID: <20240528024328.246965-29-alistair.francis@wdc.com>
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From: Yu-Ming Chang <yumin686@andestech.com>
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a regis=
ter
holding a zero value other than x0, the instruction will still attempt to w=
rite
the unmodified value back to the CSR and will cause any attendant side effe=
cts.
So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.
Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++----
target/riscv/op_helper.c | 6 ++---
3 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 12d8b5344a..1501868008 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -709,6 +709,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
void riscv_cpu_update_mask(CPURISCVState *env);
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
=20
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+ target_ulong *ret_value);
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask=
);
@@ -741,6 +743,8 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState=
*env, int csrno,
target_ulong new_value,
target_ulong write_mask);
=20
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value);
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
Int128 *ret_value,
Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 58ef7079dc..57f831fedc 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -4322,7 +4322,7 @@ static RISCVException rmw_seed(CPURISCVState *env, in=
t csrno,
=20
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
int csrno,
- bool write_mask)
+ bool write)
{
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails =
*/
bool read_only =3D get_field(csrno, 0xC00) =3D=3D 3;
@@ -4344,7 +4344,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS=
CVState *env,
}
=20
/* read / write check */
- if (write_mask && read_only) {
+ if (write && read_only) {
return RISCV_EXCP_ILLEGAL_INST;
}
=20
@@ -4431,11 +4431,22 @@ static RISCVException riscv_csrrw_do64(CPURISCVStat=
e *env, int csrno,
return RISCV_EXCP_NONE;
}
=20
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+ target_ulong *ret_value)
+{
+ RISCVException ret =3D riscv_csrrw_check(env, csrno, false);
+ if (ret !=3D RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- RISCVException ret =3D riscv_csrrw_check(env, csrno, write_mask);
+ RISCVException ret =3D riscv_csrrw_check(env, csrno, true);
if (ret !=3D RISCV_EXCP_NONE) {
return ret;
}
@@ -4483,13 +4494,45 @@ static RISCVException riscv_csrrw_do128(CPURISCVSta=
te *env, int csrno,
return RISCV_EXCP_NONE;
}
=20
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value)
+{
+ RISCVException ret;
+
+ ret =3D riscv_csrrw_check(env, csrno, false);
+ if (ret !=3D RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (csr_ops[csrno].read128) {
+ return riscv_csrrw_do128(env, csrno, ret_value,
+ int128_zero(), int128_zero());
+ }
+
+ /*
+ * Fall back to 64-bit version for now, if the 128-bit alternative isn=
't
+ * at all defined.
+ * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+ * significant), for those, this fallback is correctly handling the
+ * accesses
+ */
+ target_ulong old_value;
+ ret =3D riscv_csrrw_do64(env, csrno, &old_value,
+ (target_ulong)0,
+ (target_ulong)0);
+ if (ret =3D=3D RISCV_EXCP_NONE && ret_value) {
+ *ret_value =3D int128_make64(old_value);
+ }
+ return ret;
+}
+
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
Int128 *ret_value,
Int128 new_value, Int128 write_mask)
{
RISCVException ret;
=20
- ret =3D riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+ ret =3D riscv_csrrw_check(env, csrno, true);
if (ret !=3D RISCV_EXCP_NONE) {
return ret;
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 2baf5bc3ca..84fb2a35e5 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -51,7 +51,7 @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
}
=20
target_ulong val =3D 0;
- RISCVException ret =3D riscv_csrrw(env, csr, &val, 0, 0);
+ RISCVException ret =3D riscv_csrr(env, csr, &val);
=20
if (ret !=3D RISCV_EXCP_NONE) {
riscv_raise_exception(env, ret, GETPC());
@@ -84,9 +84,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
{
Int128 rv =3D int128_zero();
- RISCVException ret =3D riscv_csrrw_i128(env, csr, &rv,
- int128_zero(),
- int128_zero());
+ RISCVException ret =3D riscv_csrr_i128(env, csr, &rv);
=20
if (ret !=3D RISCV_EXCP_NONE) {
riscv_raise_exception(env, ret, GETPC());
--=20
2.45.1