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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Akihiko Odaki <akihiko.odaki@daynix.com>,
=?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org>,
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Subject: [PULL 26/28] riscv,
gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
Date: Tue, 28 May 2024 12:43:26 +1000
Message-ID: <20240528024328.246965-27-alistair.francis@wdc.com>
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.
Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.
While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/gdbstub.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index d0cc5762c2..c07df972f1 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUSta=
te *cs, int base_reg)
static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base=
_reg)
{
RISCVCPU *cpu =3D RISCV_CPU(cs);
- int reg_width =3D cpu->cfg.vlenb;
+ int bitsize =3D cpu->cfg.vlenb << 3;
GDBFeatureBuilder builder;
int i;
=20
@@ -298,7 +298,7 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPU=
State *cs, int base_reg)
=20
/* First define types and totals in a whole VL */
for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) {
- int count =3D reg_width / vec_lanes[i].size;
+ int count =3D bitsize / vec_lanes[i].size;
gdb_feature_builder_append_tag(
&builder, "<vector id=3D\"%s\" type=3D\"%s\" count=3D\"%d\"/>",
vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -316,7 +316,7 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPU=
State *cs, int base_reg)
/* Define vector registers */
for (i =3D 0; i < 32; i++) {
gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
- reg_width, i, "riscv_vector", "vect=
or");
+ bitsize, i, "riscv_vector", "vector=
");
}
=20
gdb_feature_builder_end(&builder);
--=20
2.45.1