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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak
breakpoint
Date: Tue, 28 May 2024 12:43:09 +1000
Message-ID: <20240528024328.246965-10-alistair.francis@wdc.com>
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Privileged spec section 4.1.9 mentions:
"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)
If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."
A similar text is found for mtval in section 3.1.16.
Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.
Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/=
insn_trans/trans_privileged.c.inc
index 620ab54eb0..bc5263a4e0 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -62,6 +62,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
if (pre =3D=3D 0x01f01013 && ebreak =3D=3D 0x00100073 && post =3D=3D 0=
x40705013) {
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
} else {
+ tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+ offsetof(CPURISCVState, badaddr));
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
}
return true;
--=20
2.45.1