From nobody Tue Nov 18 17:34:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1716797069; cv=none; d=zohomail.com; s=zohoarc; b=eTlqcZy8LY85AWbOJfy5fOa3siCL7QhXx8SOwc6HvPJkHDMm13npnP3xkqFscrE537GYr4N+mwr8D4qn+E3hp4pCVNwK1ce9pUhmKTOVQfMz7XslPlCOxjMwJTUG+w+JNOzlyRCsD9pMW3vRACWGvBfn+WWnHQyPsVqdj5wz4OA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716797069; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=0B1SVd1hxSi/X08qHYm6hJheMh++lOYnhECGKfegcJU=; b=YdK0dDUaXg9kLRbSlr/tU/nNkRvdo1pEen9G4LcJFZi4bf+BzflvzSJjZ7zlCxAF3mIl6yLfkz+l4yCKGESgd6jv7OZ7quOdY+vEdS4j0EdsTZbO90cB6cJ08nnCCJhglS3/Q9mfi4cSSr5a6Rz4l8QeEddGTK3VPZnpy8PnNCk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716797069817123.40838044302211; Mon, 27 May 2024 01:04:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBVKc-0001cI-Fx; Mon, 27 May 2024 04:03:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBVK8-0000nx-2i; Mon, 27 May 2024 04:03:16 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBVK6-0005H2-4R; Mon, 27 May 2024 04:03:15 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 27 May 2024 16:02:35 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 27 May 2024 16:02:35 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , Alistair Francis , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v4 08/16] aspeed/smc: support 64 bits dma dram address Date: Mon, 27 May 2024 16:02:22 +0800 Message-ID: <20240527080231.1576609-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240527080231.1576609-1-jamin_lin@aspeedtech.com> References: <20240527080231.1576609-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1716797366512100001 Content-Type: text/plain; charset="utf-8" AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram address, new features and update trace-event to support 64 bits dram address. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 52 +++++++++++++++++++++++++++++++------ hw/ssi/trace-events | 2 +- include/hw/ssi/aspeed_smc.h | 1 + 3 files changed, 46 insertions(+), 9 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index ffb13a12e8..df0c63469c 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -132,6 +132,9 @@ #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate= */ #define FMC_WDT2_CTRL_EN BIT(0) =20 +/* DMA DRAM Side Address High Part (AST2700) */ +#define R_DMA_DRAM_ADDR_HIGH (0x7c / 4) + /* DMA Control/Status Register */ #define R_DMA_CTRL (0x80 / 4) #define DMA_CTRL_REQUEST (1 << 31) @@ -187,6 +190,7 @@ * 0x1FFFFFF: 32M bytes */ #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask) +#define DMA_DRAM_ADDR_HIGH(val) ((val) & 0xf) #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask) #define DMA_LENGTH(val) ((val) & 0x01FFFFFF) =20 @@ -207,6 +211,7 @@ static const AspeedSegments aspeed_2500_spi2_segments[]; #define ASPEED_SMC_FEATURE_DMA 0x1 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2 #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4 +#define ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH 0x08 =20 static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc) { @@ -218,6 +223,11 @@ static inline bool aspeed_smc_has_wdt_control(const As= peedSMCClass *asc) return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL); } =20 +static inline bool aspeed_smc_has_dma64(const AspeedSMCClass *asc) +{ + return !!(asc->features & ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH); +} + #define aspeed_smc_error(fmt, ...) \ qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS= __) =20 @@ -747,6 +757,8 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr ad= dr, unsigned int size) (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_CTRL) || (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_FLASH_ADDR) || (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_DRAM_ADDR) || + (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) && + addr =3D=3D R_DMA_DRAM_ADDR_HIGH) || (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_LEN) || (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_CHECKSUM) || (addr >=3D R_SEG_ADDR0 && @@ -847,6 +859,12 @@ static bool aspeed_smc_inject_read_failure(AspeedSMCSt= ate *s) } } =20 +static uint64_t aspeed_smc_dma_dram_addr(AspeedSMCState *s) +{ + return s->regs[R_DMA_DRAM_ADDR] | + ((uint64_t) s->regs[R_DMA_DRAM_ADDR_HIGH] << 32); +} + static uint32_t aspeed_smc_dma_len(AspeedSMCState *s) { AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(s); @@ -903,24 +921,34 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s) =20 static void aspeed_smc_dma_rw(AspeedSMCState *s) { + AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(s); + uint64_t dma_dram_offset; + uint64_t dma_dram_addr; MemTxResult result; uint32_t dma_len; uint32_t data; =20 dma_len =3D aspeed_smc_dma_len(s); + dma_dram_addr =3D aspeed_smc_dma_dram_addr(s); + + if (aspeed_smc_has_dma64(asc)) { + dma_dram_offset =3D dma_dram_addr - s->dram_base; + } else { + dma_dram_offset =3D dma_dram_addr; + } =20 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? "write" : "read", s->regs[R_DMA_FLASH_ADDR], - s->regs[R_DMA_DRAM_ADDR], + dma_dram_offset, dma_len); while (dma_len) { if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { - data =3D address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_= ADDR], + data =3D address_space_ldl_le(&s->dram_as, dma_dram_offset, MEMTXATTRS_UNSPECIFIED, &result); if (result !=3D MEMTX_OK) { - aspeed_smc_error("DRAM read failed @%08x", - s->regs[R_DMA_DRAM_ADDR]); + aspeed_smc_error("DRAM read failed @%" PRIx64, + dma_dram_offset); return; } =20 @@ -940,11 +968,11 @@ static void aspeed_smc_dma_rw(AspeedSMCState *s) return; } =20 - address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], + address_space_stl_le(&s->dram_as, dma_dram_offset, data, MEMTXATTRS_UNSPECIFIED, &result); if (result !=3D MEMTX_OK) { - aspeed_smc_error("DRAM write failed @%08x", - s->regs[R_DMA_DRAM_ADDR]); + aspeed_smc_error("DRAM write failed @%" PRIx64, + dma_dram_offset); return; } } @@ -953,8 +981,12 @@ static void aspeed_smc_dma_rw(AspeedSMCState *s) * When the DMA is on-going, the DMA registers are updated * with the current working addresses and length. */ + dma_dram_offset +=3D 4; + dma_dram_addr +=3D 4; + + s->regs[R_DMA_DRAM_ADDR_HIGH] =3D dma_dram_addr >> 32; + s->regs[R_DMA_DRAM_ADDR] =3D dma_dram_addr & 0xffffffff; s->regs[R_DMA_FLASH_ADDR] +=3D 4; - s->regs[R_DMA_DRAM_ADDR] +=3D 4; dma_len -=3D 4; s->regs[R_DMA_LEN] =3D dma_len; s->regs[R_DMA_CHECKSUM] +=3D data; @@ -1107,6 +1139,9 @@ static void aspeed_smc_write(void *opaque, hwaddr add= r, uint64_t data, } else if (aspeed_smc_has_dma(asc) && addr =3D=3D R_DMA_LEN && aspeed_smc_dma_granted(s)) { s->regs[addr] =3D DMA_LENGTH(value); + } else if (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) && + addr =3D=3D R_DMA_DRAM_ADDR_HIGH) { + s->regs[addr] =3D DMA_DRAM_ADDR_HIGH(value); } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\= n", __func__, addr); @@ -1239,6 +1274,7 @@ static const VMStateDescription vmstate_aspeed_smc = =3D { =20 static Property aspeed_smc_properties[] =3D { DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, fal= se), + DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0), DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index 2d5bd2b83d..7b5ad6a939 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -6,7 +6,7 @@ aspeed_smc_do_snoop(int cs, int index, int dummies, int dat= a) "CS%d index:0x%x d aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t dat= a, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d" aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx6= 4 " size %u: 0x%" PRIx64 aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x" -aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr= , uint32_t size) "%s flash:@0x%08x dram:@0x%08x size:0x%08x" +aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint64_t dram_addr= , uint32_t size) "%s flash:@0x%08x dram:@0x%" PRIx64 " size:0x%08x" aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx= 64 " size %u: 0x%" PRIx64 aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect" =20 diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index f359ed22cc..fb36c386c0 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -76,6 +76,7 @@ struct AspeedSMCState { AddressSpace flash_as; MemoryRegion *dram_mr; AddressSpace dram_as; + uint64_t dram_base; =20 AspeedSMCFlash flashes[ASPEED_SMC_CS_MAX]; =20 --=20 2.25.1