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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1716771101456100003 Content-Type: text/plain; charset="utf-8" Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 46 ++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 8fbe6e00ce..f21cdb45ea 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -2725,39 +2725,41 @@ void helper_xsaveopt(CPUX86State *env, target_ulong= ptr, uint64_t rfbm) do_xsave(env, ptr, rfbm, inuse, inuse, GETPC()); } =20 -static void do_xrstor_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra) +static void do_xrstor_fpu(X86Access *ac, target_ulong ptr) { + CPUX86State *env =3D ac->env; int i, fpuc, fpus, fptag; target_ulong addr; - X86Access ac; =20 - fpuc =3D cpu_lduw_data_ra(env, ptr + XO(legacy.fcw), ra); - fpus =3D cpu_lduw_data_ra(env, ptr + XO(legacy.fsw), ra); - fptag =3D cpu_lduw_data_ra(env, ptr + XO(legacy.ftw), ra); + fpuc =3D access_ldw(ac, ptr + XO(legacy.fcw)); + fpus =3D access_ldw(ac, ptr + XO(legacy.fsw)); + fptag =3D access_ldw(ac, ptr + XO(legacy.ftw)); cpu_set_fpuc(env, fpuc); cpu_set_fpus(env, fpus); + fptag ^=3D 0xff; for (i =3D 0; i < 8; i++) { env->fptags[i] =3D ((fptag >> i) & 1); } =20 addr =3D ptr + XO(legacy.fpregs); - access_prepare(&ac, env, addr, 8 * 16, MMU_DATA_LOAD, ra); =20 for (i =3D 0; i < 8; i++) { - floatx80 tmp =3D do_fldt(&ac, addr); + floatx80 tmp =3D do_fldt(ac, addr); ST(i) =3D tmp; addr +=3D 16; } } =20 -static void do_xrstor_mxcsr(CPUX86State *env, target_ulong ptr, uintptr_t = ra) +static void do_xrstor_mxcsr(X86Access *ac, target_ulong ptr) { - cpu_set_mxcsr(env, cpu_ldl_data_ra(env, ptr + XO(legacy.mxcsr), ra)); + CPUX86State *env =3D ac->env; + cpu_set_mxcsr(env, access_ldl(ac, ptr + XO(legacy.mxcsr))); } =20 -static void do_xrstor_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra) +static void do_xrstor_sse(X86Access *ac, target_ulong ptr) { + CPUX86State *env =3D ac->env; int i, nb_xmm_regs; target_ulong addr; =20 @@ -2769,8 +2771,8 @@ static void do_xrstor_sse(CPUX86State *env, target_ul= ong ptr, uintptr_t ra) =20 addr =3D ptr + XO(legacy.xmm_regs); for (i =3D 0; i < nb_xmm_regs; i++) { - env->xmm_regs[i].ZMM_Q(0) =3D cpu_ldq_data_ra(env, addr, ra); - env->xmm_regs[i].ZMM_Q(1) =3D cpu_ldq_data_ra(env, addr + 8, ra); + env->xmm_regs[i].ZMM_Q(0) =3D access_ldq(ac, addr); + env->xmm_regs[i].ZMM_Q(1) =3D access_ldq(ac, addr + 8); addr +=3D 16; } } @@ -2850,20 +2852,24 @@ static void do_xrstor_pkru(CPUX86State *env, target= _ulong ptr, uintptr_t ra) =20 static void do_fxrstor(CPUX86State *env, target_ulong ptr, uintptr_t ra) { + X86Access ac; + /* The operand must be 16 byte aligned */ if (ptr & 0xf) { raise_exception_ra(env, EXCP0D_GPF, ra); } =20 - do_xrstor_fpu(env, ptr, ra); + access_prepare(&ac, env, ptr, sizeof(X86LegacyXSaveArea), + MMU_DATA_LOAD, ra); + do_xrstor_fpu(&ac, ptr); =20 if (env->cr[4] & CR4_OSFXSR_MASK) { - do_xrstor_mxcsr(env, ptr, ra); + do_xrstor_mxcsr(&ac, ptr); /* Fast FXRSTOR leaves out the XMM registers */ if (!(env->efer & MSR_EFER_FFXSR) || (env->hflags & HF_CPL_MASK) || !(env->hflags & HF_LMA_MASK)) { - do_xrstor_sse(env, ptr, ra); + do_xrstor_sse(&ac, ptr); } } } @@ -2876,6 +2882,7 @@ void helper_fxrstor(CPUX86State *env, target_ulong pt= r) static void do_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm, u= intptr_t ra) { uint64_t xstate_bv, xcomp_bv, reserve0; + X86Access ac; =20 rfbm &=3D env->xcr0; =20 @@ -2914,9 +2921,12 @@ static void do_xrstor(CPUX86State *env, target_ulong= ptr, uint64_t rfbm, uintptr raise_exception_ra(env, EXCP0D_GPF, ra); } =20 + access_prepare(&ac, env, ptr, sizeof(X86LegacyXSaveArea), + MMU_DATA_LOAD, ra); + if (rfbm & XSTATE_FP_MASK) { if (xstate_bv & XSTATE_FP_MASK) { - do_xrstor_fpu(env, ptr, ra); + do_xrstor_fpu(&ac, ptr); } else { do_fninit(env); memset(env->fpregs, 0, sizeof(env->fpregs)); @@ -2925,9 +2935,9 @@ static void do_xrstor(CPUX86State *env, target_ulong = ptr, uint64_t rfbm, uintptr if (rfbm & XSTATE_SSE_MASK) { /* Note that the standard form of XRSTOR loads MXCSR from memory whether or not the XSTATE_BV bit is set. */ - do_xrstor_mxcsr(env, ptr, ra); + do_xrstor_mxcsr(&ac, ptr); if (xstate_bv & XSTATE_SSE_MASK) { - do_xrstor_sse(env, ptr, ra); + do_xrstor_sse(&ac, ptr); } else { do_clear_sse(env); } --=20 2.34.1