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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fd6d7598sm3942958b3a.220.2024.05.26.17.50.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 17:50:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716771008; x=1717375808; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V9YixNcV0VmfO6aoH+tEoVfr0IpNqbjtk188TFL76t0=; b=GoWMMoizyYsYqyOGLNPVZ6RtYYfyBDzY13BZprKBLEs3SXbKaKqMRaM+CltxyT7wFB b0rtnDvMuMEufdhtDzudXyBMAIOdJJcKJTq2hoPyWUlt1K5r+WJoB253JF7nIRgZlFmV JPX25v+rvxQE/cFs5X8g3BSA1QkAp+qt6FtoatRaHhEHQ29rcsdvHDS9roYQKfm8uGju b1dElAQR9QSfkO3Ne+d6mAMBHfgQJ0K+0mtjA1f5buqDLJEC6uld6/jEwRHlOkaRAImt 3He3INVC4HPfTsf44cti0TeR9wo6Kdb/WfF/PwkQGnkYf+7RfIQhY/WQ6njotLgJzlfV G0DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716771008; x=1717375808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V9YixNcV0VmfO6aoH+tEoVfr0IpNqbjtk188TFL76t0=; b=WvF4M9HQ9Ob7eEs1JB+akftTblHnX9EiGd9vFZsakr3laN/MNYeVjZ/NT+PY2NV540 nvCvH9zt42HC/OCwj23etvsMF4fP70HF2r6p71imGFnD6kqXNcHW1A2ijJQbxb9VNdSZ 9oons4LvxggU0aGmRCPihBNw8okuDAey5ji4byLeerIN4/M1uM241qx7Xeg92tGEiHnk G7OYMFkKeo52CJh2QpoX3ytIx/mF7P52U/SjQUbyIEGu0uGnD3CICMN6P+YczazRMPc2 IiRY6/jHWbearo4PCnp9iqk4Lw1M3os1HzKFQtW3SFkjcNIUw1fBCG1DA/9NgC+3AuoS HvDA== X-Gm-Message-State: AOJu0Yx2SDOLoKq3n4TXLh56zkC7RXyoVhIEAmU8B4J77S5izb+J2Z1J PL/9ICCDmQkNFaXO1MOMt2RtzBdpV2zjNYo6L4cwgkWUlBhiPEWJp0fR+Hw/BAl6GHPtd19WrcF e X-Google-Smtp-Source: AGHT+IE2edoz8OgKOwF4Lb1hZQ3L930fYgxvhhhjsckqpfaU87MpRT+l3olLioSy9pTRlKryXN3uKw== X-Received: by 2002:a05:6a00:e13:b0:6ec:d3a6:801 with SMTP id d2e1a72fcca58-6f8e9fbffd2mr10122643b3a.11.1716771007882; Sun, 26 May 2024 17:50:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Paolo Bonzini Subject: [PULL 07/28] target/i386: Convert do_xsave_{fpu, mxcr, sse} to X86Access Date: Sun, 26 May 2024 17:49:40 -0700 Message-Id: <20240527005001.642825-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240527005001.642825-1-richard.henderson@linaro.org> References: <20240527005001.642825-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1716771370346100003 Content-Type: text/plain; charset="utf-8" Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 52 +++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 21 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index df12eac71e..8fbe6e00ce 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -2519,11 +2519,11 @@ void helper_frstor(CPUX86State *env, target_ulong p= tr, int data32) =20 #define XO(X) offsetof(X86XSaveArea, X) =20 -static void do_xsave_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra) +static void do_xsave_fpu(X86Access *ac, target_ulong ptr) { + CPUX86State *env =3D ac->env; int fpus, fptag, i; target_ulong addr; - X86Access ac; =20 fpus =3D (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; fptag =3D 0; @@ -2531,35 +2531,37 @@ static void do_xsave_fpu(CPUX86State *env, target_u= long ptr, uintptr_t ra) fptag |=3D (env->fptags[i] << i); } =20 - cpu_stw_data_ra(env, ptr + XO(legacy.fcw), env->fpuc, ra); - cpu_stw_data_ra(env, ptr + XO(legacy.fsw), fpus, ra); - cpu_stw_data_ra(env, ptr + XO(legacy.ftw), fptag ^ 0xff, ra); + access_stw(ac, ptr + XO(legacy.fcw), env->fpuc); + access_stw(ac, ptr + XO(legacy.fsw), fpus); + access_stw(ac, ptr + XO(legacy.ftw), fptag ^ 0xff); =20 /* In 32-bit mode this is eip, sel, dp, sel. In 64-bit mode this is rip, rdp. But in either case we don't write actual data, just zeros. */ - cpu_stq_data_ra(env, ptr + XO(legacy.fpip), 0, ra); /* eip+sel; rip */ - cpu_stq_data_ra(env, ptr + XO(legacy.fpdp), 0, ra); /* edp+sel; rdp */ + access_stq(ac, ptr + XO(legacy.fpip), 0); /* eip+sel; rip */ + access_stq(ac, ptr + XO(legacy.fpdp), 0); /* edp+sel; rdp */ =20 addr =3D ptr + XO(legacy.fpregs); - access_prepare(&ac, env, addr, 8 * 16, MMU_DATA_STORE, ra); =20 for (i =3D 0; i < 8; i++) { floatx80 tmp =3D ST(i); - do_fstt(&ac, addr, tmp); + do_fstt(ac, addr, tmp); addr +=3D 16; } } =20 -static void do_xsave_mxcsr(CPUX86State *env, target_ulong ptr, uintptr_t r= a) +static void do_xsave_mxcsr(X86Access *ac, target_ulong ptr) { + CPUX86State *env =3D ac->env; + update_mxcsr_from_sse_status(env); - cpu_stl_data_ra(env, ptr + XO(legacy.mxcsr), env->mxcsr, ra); - cpu_stl_data_ra(env, ptr + XO(legacy.mxcsr_mask), 0x0000ffff, ra); + access_stl(ac, ptr + XO(legacy.mxcsr), env->mxcsr); + access_stl(ac, ptr + XO(legacy.mxcsr_mask), 0x0000ffff); } =20 -static void do_xsave_sse(CPUX86State *env, target_ulong ptr, uintptr_t ra) +static void do_xsave_sse(X86Access *ac, target_ulong ptr) { + CPUX86State *env =3D ac->env; int i, nb_xmm_regs; target_ulong addr; =20 @@ -2571,8 +2573,8 @@ static void do_xsave_sse(CPUX86State *env, target_ulo= ng ptr, uintptr_t ra) =20 addr =3D ptr + XO(legacy.xmm_regs); for (i =3D 0; i < nb_xmm_regs; i++) { - cpu_stq_data_ra(env, addr, env->xmm_regs[i].ZMM_Q(0), ra); - cpu_stq_data_ra(env, addr + 8, env->xmm_regs[i].ZMM_Q(1), ra); + access_stq(ac, addr, env->xmm_regs[i].ZMM_Q(0)); + access_stq(ac, addr + 8, env->xmm_regs[i].ZMM_Q(1)); addr +=3D 16; } } @@ -2619,20 +2621,24 @@ static void do_xsave_pkru(CPUX86State *env, target_= ulong ptr, uintptr_t ra) =20 static void do_fxsave(CPUX86State *env, target_ulong ptr, uintptr_t ra) { + X86Access ac; + /* The operand must be 16 byte aligned */ if (ptr & 0xf) { raise_exception_ra(env, EXCP0D_GPF, ra); } =20 - do_xsave_fpu(env, ptr, ra); + access_prepare(&ac, env, ptr, sizeof(X86LegacyXSaveArea), + MMU_DATA_STORE, ra); + do_xsave_fpu(&ac, ptr); =20 if (env->cr[4] & CR4_OSFXSR_MASK) { - do_xsave_mxcsr(env, ptr, ra); + do_xsave_mxcsr(&ac, ptr); /* Fast FXSAVE leaves out the XMM registers */ if (!(env->efer & MSR_EFER_FFXSR) || (env->hflags & HF_CPL_MASK) || !(env->hflags & HF_LMA_MASK)) { - do_xsave_sse(env, ptr, ra); + do_xsave_sse(&ac, ptr); } } } @@ -2660,6 +2666,7 @@ static void do_xsave(CPUX86State *env, target_ulong p= tr, uint64_t rfbm, uint64_t inuse, uint64_t opt, uintptr_t ra) { uint64_t old_bv, new_bv; + X86Access ac; =20 /* The OS must have enabled XSAVE. */ if (!(env->cr[4] & CR4_OSXSAVE_MASK)) { @@ -2675,15 +2682,18 @@ static void do_xsave(CPUX86State *env, target_ulong= ptr, uint64_t rfbm, rfbm &=3D env->xcr0; opt &=3D rfbm; =20 + access_prepare(&ac, env, ptr, sizeof(X86LegacyXSaveArea), + MMU_DATA_STORE, ra); + if (opt & XSTATE_FP_MASK) { - do_xsave_fpu(env, ptr, ra); + do_xsave_fpu(&ac, ptr); } if (rfbm & XSTATE_SSE_MASK) { /* Note that saving MXCSR is not suppressed by XSAVEOPT. */ - do_xsave_mxcsr(env, ptr, ra); + do_xsave_mxcsr(&ac, ptr); } if (opt & XSTATE_SSE_MASK) { - do_xsave_sse(env, ptr, ra); + do_xsave_sse(&ac, ptr); } if (opt & XSTATE_YMM_MASK) { do_xsave_ymmh(env, ptr + XO(avx_state), ra); --=20 2.34.1