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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fd6d7598sm3942958b3a.220.2024.05.26.17.50.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 17:50:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716771003; x=1717375803; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XQrV4UMaEBl22gT4Xij+bzAgjXuhBjByp/7UaStu/qs=; b=Hjf8t2TzS7HfCn3W4MkT5uTUQQkEASL3ORQm8fP/iNYIrSUN/FmlrLk4CbhyUT0SWd UNaE99sFYGOA/Tt9FktRzcFh3UcxqfoO9C7sEG8RukQjjMcUcL8z95GzcCiLn5/ULFcy JIV6JWNtAPpubrSVnuH8dVUiYqIwsc3m/rCQXan7sYWxxBeRP79bJr3HfSu08UHMMg70 K0r9rGnvxrY3r3tM1Jj6SuP2jSsfSXgqTd2r0dZM9+6J27rq698q188sjFcsQUvQxvj0 GuozBTS4sUAiiYEJgmwGMqiVnVZ5aEfnhaZr6P2zIjXR3CKmnSrh5QRI3yKFKJuomNZl sZHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716771003; x=1717375803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XQrV4UMaEBl22gT4Xij+bzAgjXuhBjByp/7UaStu/qs=; b=GnxU3wjZhvAER4ux+Ezb7u4eXbRx22qynKfKEbwA/5iMu9PEjFwbaE2OXemyj+Vjcl cmQ1MmotH4fyZ4c8Nk3cSwdX5mV2C+kYWDyZXEDlCQSL+gRf4NvfB+SXFu0o4RqNWUQR QRdE95j+z4tcxoJ6wC9HgDlTCD2WO0wW+dvDsy0QI6NA8y3PPd/hBU6iOhlwNfVT/w+7 CxvOLgH+bictrZkh/LxAsvIf3boh6qYI+7PhPZRxPu3v6Ts7G6q7llW8VSZdsTpEOlxW x4cR/Q0C0zLZhttQ5o/RWVo6IjxKHr5P+fslm/s70/3bdo/YXmO5YSnxax84118ZGh1S Mlcg== X-Gm-Message-State: AOJu0Yyz983z5Nprg0pk03EgyS8Q1H7p93iOxXDweazTQNG/1n8bOzrg W4NUmqwZZGX+16SZT/xKbqUawNBO78cLjxdsqwSN2ZkiFx8a9BRei9zKgcV3xDqTmxGxbb6ctI2 J X-Google-Smtp-Source: AGHT+IHDrIobzXa8wXZ1pbgkcgMPfKLQ0jH2r7xPa6m/K5gjT+jYw7xa38L4D7359lvasNSTZpchmw== X-Received: by 2002:a05:6808:144:b0:3c6:efde:7a45 with SMTP id 5614622812f47-3d1a7a2dd0cmr8372080b6e.50.1716771003367; Sun, 26 May 2024 17:50:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Paolo Bonzini Subject: [PULL 01/28] target/i386: Add tcg/access.[ch] Date: Sun, 26 May 2024 17:49:34 -0700 Message-Id: <20240527005001.642825-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240527005001.642825-1-richard.henderson@linaro.org> References: <20240527005001.642825-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716771051489100006 Content-Type: text/plain; charset="utf-8" Provide a method to amortize page lookup across large blocks. Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target/i386/tcg/access.h | 40 +++++++++ target/i386/tcg/access.c | 169 ++++++++++++++++++++++++++++++++++++ target/i386/tcg/meson.build | 1 + 3 files changed, 210 insertions(+) create mode 100644 target/i386/tcg/access.h create mode 100644 target/i386/tcg/access.c diff --git a/target/i386/tcg/access.h b/target/i386/tcg/access.h new file mode 100644 index 0000000000..d70808a3a3 --- /dev/null +++ b/target/i386/tcg/access.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Access guest memory in blocks. */ + +#ifndef X86_TCG_ACCESS_H +#define X86_TCG_ACCESS_H + +/* An access covers at most sizeof(X86XSaveArea), at most 2 pages. */ +typedef struct X86Access { + target_ulong vaddr; + void *haddr1; + void *haddr2; + uint16_t size; + uint16_t size1; + /* + * If we can't access the host page directly, we'll have to do I/O acc= ess + * via ld/st helpers. These are internal details, so we store the rest + * to do the access here instead of passing it around in the helpers. + */ + int mmu_idx; + CPUX86State *env; + uintptr_t ra; +} X86Access; + +void access_prepare_mmu(X86Access *ret, CPUX86State *env, + vaddr vaddr, unsigned size, + MMUAccessType type, int mmu_idx, uintptr_t ra); +void access_prepare(X86Access *ret, CPUX86State *env, vaddr vaddr, + unsigned size, MMUAccessType type, uintptr_t ra); + +uint8_t access_ldb(X86Access *ac, vaddr addr); +uint16_t access_ldw(X86Access *ac, vaddr addr); +uint32_t access_ldl(X86Access *ac, vaddr addr); +uint64_t access_ldq(X86Access *ac, vaddr addr); + +void access_stb(X86Access *ac, vaddr addr, uint8_t val); +void access_stw(X86Access *ac, vaddr addr, uint16_t val); +void access_stl(X86Access *ac, vaddr addr, uint32_t val); +void access_stq(X86Access *ac, vaddr addr, uint64_t val); + +#endif diff --git a/target/i386/tcg/access.c b/target/i386/tcg/access.c new file mode 100644 index 0000000000..56a1181ea5 --- /dev/null +++ b/target/i386/tcg/access.c @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Access guest memory in blocks. */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/cpu_ldst.h" +#include "exec/exec-all.h" +#include "access.h" + + +void access_prepare_mmu(X86Access *ret, CPUX86State *env, + vaddr vaddr, unsigned size, + MMUAccessType type, int mmu_idx, uintptr_t ra) +{ + int size1, size2; + void *haddr1, *haddr2; + + assert(size > 0 && size <=3D TARGET_PAGE_SIZE); + + size1 =3D MIN(size, -(vaddr | TARGET_PAGE_MASK)), + size2 =3D size - size1; + + memset(ret, 0, sizeof(*ret)); + ret->vaddr =3D vaddr; + ret->size =3D size; + ret->size1 =3D size1; + ret->mmu_idx =3D mmu_idx; + ret->env =3D env; + ret->ra =3D ra; + + haddr1 =3D probe_access(env, vaddr, size1, type, mmu_idx, ra); + ret->haddr1 =3D haddr1; + + if (unlikely(size2)) { + haddr2 =3D probe_access(env, vaddr + size1, size2, type, mmu_idx, = ra); + if (haddr2 =3D=3D haddr1 + size1) { + ret->size1 =3D size; + } else { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + ret->haddr2 =3D haddr2; +#endif + } + } +} + +void access_prepare(X86Access *ret, CPUX86State *env, vaddr vaddr, + unsigned size, MMUAccessType type, uintptr_t ra) +{ + int mmu_idx =3D cpu_mmu_index(env_cpu(env), false); + access_prepare_mmu(ret, env, vaddr, size, type, mmu_idx, ra); +} + +static void *access_ptr(X86Access *ac, vaddr addr, unsigned len) +{ + vaddr offset =3D addr - ac->vaddr; + + assert(addr >=3D ac->vaddr); + +#ifdef CONFIG_USER_ONLY + assert(offset <=3D ac->size1 - len); + return ac->haddr1 + offset; +#else + if (likely(offset <=3D ac->size1 - len)) { + return ac->haddr1 + offset; + } + assert(offset <=3D ac->size - len); + /* + * If the address is not naturally aligned, it might span both pages. + * Only return ac->haddr2 if the area is entirely within the second pa= ge, + * otherwise fall back to slow accesses. + */ + if (likely(offset >=3D ac->size1)) { + return ac->haddr2 + (offset - ac->size1); + } + return NULL; +#endif +} + +#ifdef CONFIG_USER_ONLY +# define test_ptr(p) true +#else +# define test_ptr(p) likely(p) +#endif + +uint8_t access_ldb(X86Access *ac, vaddr addr) +{ + void *p =3D access_ptr(ac, addr, sizeof(uint8_t)); + + if (test_ptr(p)) { + return ldub_p(p); + } + return cpu_ldub_mmuidx_ra(ac->env, addr, ac->mmu_idx, ac->ra); +} + +uint16_t access_ldw(X86Access *ac, vaddr addr) +{ + void *p =3D access_ptr(ac, addr, sizeof(uint16_t)); + + if (test_ptr(p)) { + return lduw_le_p(p); + } + return cpu_lduw_le_mmuidx_ra(ac->env, addr, ac->mmu_idx, ac->ra); +} + +uint32_t access_ldl(X86Access *ac, vaddr addr) +{ + void *p =3D access_ptr(ac, addr, sizeof(uint32_t)); + + if (test_ptr(p)) { + return ldl_le_p(p); + } + return cpu_ldl_le_mmuidx_ra(ac->env, addr, ac->mmu_idx, ac->ra); +} + +uint64_t access_ldq(X86Access *ac, vaddr addr) +{ + void *p =3D access_ptr(ac, addr, sizeof(uint64_t)); + + if (test_ptr(p)) { + return ldq_le_p(p); + } + return cpu_ldq_le_mmuidx_ra(ac->env, addr, ac->mmu_idx, ac->ra); +} + +void access_stb(X86Access *ac, vaddr addr, uint8_t val) +{ + void *p =3D access_ptr(ac, addr, sizeof(uint8_t)); + + if (test_ptr(p)) { + stb_p(p, val); + } else { + cpu_stb_mmuidx_ra(ac->env, addr, val, ac->mmu_idx, ac->ra); + } +} + +void access_stw(X86Access *ac, vaddr addr, uint16_t val) +{ + void *p =3D access_ptr(ac, addr, sizeof(uint16_t)); + + if (test_ptr(p)) { + stw_le_p(p, val); + } else { + cpu_stw_le_mmuidx_ra(ac->env, addr, val, ac->mmu_idx, ac->ra); + } +} + +void access_stl(X86Access *ac, vaddr addr, uint32_t val) +{ + void *p =3D access_ptr(ac, addr, sizeof(uint32_t)); + + if (test_ptr(p)) { + stl_le_p(p, val); + } else { + cpu_stl_le_mmuidx_ra(ac->env, addr, val, ac->mmu_idx, ac->ra); + } +} + +void access_stq(X86Access *ac, vaddr addr, uint64_t val) +{ + void *p =3D access_ptr(ac, addr, sizeof(uint64_t)); + + if (test_ptr(p)) { + stq_le_p(p, val); + } else { + cpu_stq_le_mmuidx_ra(ac->env, addr, val, ac->mmu_idx, ac->ra); + } +} diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build index f9110e890c..1105b35d92 100644 --- a/target/i386/tcg/meson.build +++ b/target/i386/tcg/meson.build @@ -1,4 +1,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( + 'access.c', 'bpt_helper.c', 'cc_helper.c', 'excp_helper.c', --=20 2.34.1