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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716771274094100011 Content-Type: text/plain; charset="utf-8" Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- linux-user/i386/signal.c | 43 +++++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index 5b1c570bff..3271ebd333 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -34,6 +34,23 @@ struct target_fpreg { uint16_t exponent; }; =20 +/* Legacy x87 fpu state format for FSAVE/FRESTOR. */ +struct target_fregs_state { + uint32_t cwd; + uint32_t swd; + uint32_t twd; + uint32_t fip; + uint32_t fcs; + uint32_t foo; + uint32_t fos; + struct target_fpreg st[8]; + + /* Software status information [not touched by FSAVE]. */ + uint16_t status; + uint16_t magic; /* 0xffff: FPU data only, 0x0000: FXSR FPU data */ +}; +QEMU_BUILD_BUG_ON(sizeof(struct target_fregs_state) !=3D 32 + 80); + struct target_fpx_sw_bytes { uint32_t magic1; uint32_t extended_size; @@ -44,29 +61,19 @@ struct target_fpx_sw_bytes { QEMU_BUILD_BUG_ON(sizeof(struct target_fpx_sw_bytes) !=3D 12*4); =20 struct target_fpstate_32 { - /* Regular FPU environment */ - uint32_t cw; - uint32_t sw; - uint32_t tag; - uint32_t ipoff; - uint32_t cssel; - uint32_t dataoff; - uint32_t datasel; - struct target_fpreg st[8]; - uint16_t status; - uint16_t magic; /* 0xffff =3D regular FPU data only */ - X86LegacyXSaveArea fxsave; + struct target_fregs_state fpstate; + X86LegacyXSaveArea fxstate; }; =20 /* * For simplicity, setup_frame aligns struct target_fpstate_32 to * 16 bytes, so ensure that the FXSAVE area is also aligned. */ -QEMU_BUILD_BUG_ON(offsetof(struct target_fpstate_32, fxsave) & 15); +QEMU_BUILD_BUG_ON(offsetof(struct target_fpstate_32, fxstate) & 15); =20 #ifndef TARGET_X86_64 # define target_fpstate target_fpstate_32 -# define TARGET_FPSTATE_FXSAVE_OFFSET offsetof(struct target_fpstate_32, f= xsave) +# define TARGET_FPSTATE_FXSAVE_OFFSET offsetof(struct target_fpstate_32, f= xstate) #else # define target_fpstate X86LegacyXSaveArea # define TARGET_FPSTATE_FXSAVE_OFFSET 0 @@ -279,15 +286,15 @@ static void setup_sigcontext(struct target_sigcontext= *sc, __put_user(env->segs[R_SS].selector, (unsigned int *)&sc->ss); =20 cpu_x86_fsave(env, fpstate_addr, 1); - fpstate->status =3D fpstate->sw; + fpstate->fpstate.status =3D fpstate->fpstate.swd; if (!(env->features[FEAT_1_EDX] & CPUID_FXSR)) { magic =3D 0xffff; } else { - xsave_sigcontext(env, &fpstate->fxsave, + xsave_sigcontext(env, &fpstate->fxstate, fpstate_addr + TARGET_FPSTATE_FXSAVE_OFFSET); magic =3D 0; } - __put_user(magic, &fpstate->magic); + __put_user(magic, &fpstate->fpstate.magic); #else __put_user(env->regs[R_EDI], &sc->rdi); __put_user(env->regs[R_ESI], &sc->rsi); @@ -623,7 +630,7 @@ restore_sigcontext(CPUX86State *env, struct target_sigc= ontext *sc) cpu_x86_frstor(env, fpstate_addr, 1); err =3D 0; } else { - err =3D xrstor_sigcontext(env, &fpstate->fxsave, + err =3D xrstor_sigcontext(env, &fpstate->fxstate, fpstate_addr + TARGET_FPSTATE_FXSAVE_O= FFSET); } #else --=20 2.34.1