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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2bf5f6155b6sm4943761a91.29.2024.05.26.12.36.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:36:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752201; x=1717357001; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lJ/MHrlbj4C0ri8M58dDIQBRERSolyRdsK7MrfghSiM=; b=nq0FxlZEqr/t31yZa29s+GfN6dTQo9zAUzTFARgn4hQT5N7DBPLbOcgz/FnPa3EXKZ PBAvDmqsgzDvn4MRudq+dNox0OqoC9dHnF9eByEk3qGUIuoDKk81xsjSm7uzvB4Lz8So 2vP3bHpZzbIVF6OcwoGOxchPlG9G1B/iWZzMAgzhb0kvxHlw/uM/WsdtvqBCpqE5ZgS5 MYjrFBPDYgAhh2VRp9Km0LKTCNxmiutCnMOAjskp1gNYXZRiiWBibAR73JDwkeGy6Kvx XVluT8fIgkqWPY/NSYGiCkY7Un4c9oQfv7l4+8oD1lWxcAiTuV9Ppsyk3heK6xrP0BGp 35ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752201; x=1717357001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lJ/MHrlbj4C0ri8M58dDIQBRERSolyRdsK7MrfghSiM=; b=pMTNybWyVAs+2id6On8pRGXxDcwbS28giPERsaNw/U5jJmMD1kzSxL939Vl6l4NrnQ ACmLLepzY7qGEFagq7/FnFo8VmBfAMMefH779eLrKN9dOiRcM/0SVh/DEQhTeCmBI7gJ 5C0JZDlFSj8Zc4bP8XlSS4PMsAjJmdZw/oM0W3v8Tl6E8f/FyzmhAaQX+B/YAFSQHT0S qpJ2LIDfhDtnJu09V3YB5X7x2vTpWJPHXthFkS2Z+Pot0ctd60LT6nRecsMdqLvNS8lI QdecY5tnFoWyH7TdYZi+z4x4oNDXOzJ4JhLVZDNHgNxby4NL0VDNwZCIH11oNnp1+moP PsRg== X-Gm-Message-State: AOJu0Yz0LpW9P+vR8yZKjPHOun1cnZacQnT7LyaOW+EMhcRE7ER9bOqb 8Wc+68CbznInFXI0x2qTuz8U4SWmYZAG+VreQAMocU5OPInga6PzNmxdwnZsVdX1r7klMnmRoJg C X-Google-Smtp-Source: AGHT+IEuRBgGmWscYtwocPNIPowL01rJk2YieL0kPTmo7w8Ag6znCLLny9Jxsiew+TjXbFPfXWa1Ew== X-Received: by 2002:a17:90b:3709:b0:2ba:e4d:d2b0 with SMTP id 98e67ed59e1d1-2bf5e137071mr6968323a91.3.1716752200834; Sun, 26 May 2024 12:36:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH RISU v2 02/13] Build elf test cases instead of raw binaries Date: Sun, 26 May 2024 12:36:26 -0700 Message-Id: <20240526193637.459064-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526193637.459064-1-richard.henderson@linaro.org> References: <20240526193637.459064-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752287489100001 For test_arch64.s and test_arm.s, use '.inst' so that the risu control insns are marked as instructions for disassembly. For test_i386.S, split the data to be loaded into the data section; fix an error aligning the data: 16 not 2**16. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- Makefile | 19 ++++++++++--------- test.ld | 12 ++++++++++++ test_aarch64.s | 4 ++-- test_arm.s | 16 +++++++++++----- test_i386.S | 4 +++- 5 files changed, 38 insertions(+), 17 deletions(-) create mode 100644 test.ld diff --git a/Makefile b/Makefile index ad7f879..2bd08aa 100644 --- a/Makefile +++ b/Makefile @@ -22,7 +22,8 @@ ALL_CFLAGS =3D -Wall -D_GNU_SOURCE -DARCH=3D$(ARCH) -U$(A= RCH) $(BUILD_INC) $(CFLAGS) PROG=3Drisu SRCS=3Drisu.c comms.c risu_$(ARCH).c risu_reginfo_$(ARCH).c HDRS=3Drisu.h risu_reginfo_$(ARCH).h -BINS=3Dtest_$(ARCH).bin +BINO=3Dtest_$(ARCH).o +BINE=3Dtest_$(ARCH).elf =20 # For dumping test patterns RISU_BINS=3D$(wildcard *.risu.bin) @@ -30,7 +31,7 @@ RISU_ASMS=3D$(patsubst %.bin,%.asm,$(RISU_BINS)) =20 OBJS=3D$(SRCS:.c=3D.o) =20 -all: $(PROG) $(BINS) +all: $(PROG) $(BINE) =20 dump: $(RISU_ASMS) =20 @@ -43,17 +44,17 @@ $(PROG): $(OBJS) %.o: %.c $(HDRS) $(CC) $(CPPFLAGS) $(ALL_CFLAGS) -o $@ -c $< =20 -%_$(ARCH).bin: %_$(ARCH).elf - $(OBJCOPY) -O binary $< $@ +%_$(ARCH).o: %_$(ARCH).s + $(CC) -o $@ -c $< =20 -%_$(ARCH).elf: %_$(ARCH).s - $(AS) -o $@ $< - -%_$(ARCH).elf: %_$(ARCH).S +%_$(ARCH).o: %_$(ARCH).S $(CC) $(CPPFLAGS) -o $@ -c $< =20 +%_$(ARCH).elf: test.ld %_$(ARCH).o + $(LD) -o $@ -T $^ + clean: - rm -f $(PROG) $(OBJS) $(BINS) + rm -f $(PROG) $(OBJS) $(BINO) $(BINE) =20 distclean: clean rm -f config.h Makefile.in diff --git a/test.ld b/test.ld new file mode 100644 index 0000000..eb0a76a --- /dev/null +++ b/test.ld @@ -0,0 +1,12 @@ +ENTRY(start) + +PHDRS { + text PT_LOAD FILEHDR PHDRS; +} + +SECTIONS { + . =3D SIZEOF_HEADERS; + PROVIDE(start =3D .); + .text : { *(.text) } :text + .data : { *(.data) } :text +} diff --git a/test_aarch64.s b/test_aarch64.s index f75d588..88902c6 100644 --- a/test_aarch64.s +++ b/test_aarch64.s @@ -80,6 +80,6 @@ fmov d31, #31.0 /* do compare. * The manual says instr with bits (28,27) =3D=3D 0 0 are UNALLOCATED */ -.int 0x00005af0 +.inst 0x00005af0 /* exit test */ -.int 0x00005af1 +.inst 0x00005af1 diff --git a/test_arm.s b/test_arm.s index 49552f2..62582e7 100644 --- a/test_arm.s +++ b/test_arm.s @@ -9,20 +9,26 @@ * Peter Maydell (Linaro) - initial implementation *************************************************************************= ******/ =20 +.text + /* magic instruction to force ARM mode whether we were in ARM or Thumb bef= ore */ -.int 0xe0004778 +.inst 0xe0004778 + /* Initialise the gp regs */ add r0, pc, #4 ldmia r0, {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r14} -b next +b 1f + .int 0,1,2,3,4,5,6,7,8,9,10,11,12,14 -next: + +1: msr CPSR_fs, #0 + /* do compare. * The space 0xE7F___F_ is guaranteed to always UNDEF * and not to be allocated for insns in future architecture * revisions. */ -.int 0xe7fe5af0 +.inst 0xe7fe5af0 /* exit test */ -.int 0xe7fe5af1 +.inst 0xe7fe5af1 diff --git a/test_i386.S b/test_i386.S index 05344d7..2e2b090 100644 --- a/test_i386.S +++ b/test_i386.S @@ -13,6 +13,7 @@ =20 /* Initialise the registers to avoid spurious mismatches */ =20 +.text #ifdef __x86_64__ #define BASE %rax lea 2f(%rip), BASE @@ -71,7 +72,8 @@ /* exit test */ ud1 %ecx, %eax =20 - .p2align 16 +.data + .balign 16 2: .set i, 0 .rept 256 --=20 2.34.1