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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fcfe648bsm3457182b3a.168.2024.05.26.05.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 05:26:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716726407; x=1717331207; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KxtsOOjIQD+5fdn20u7+8eRQWnzhtvstNVtvMn8QGkc=; b=jmpFeL9fyXA8YIaXmf551CL2fn5t4wvzJ8su/kGHSln1nuzmtgBU0JZ2ak3n44XQ4A WABmctLi54bdrs6dvIs1u4CMzwLqv84qBBRH/2V2mmCNygk+GsYGDE44mGnD6q9EaPPj mHt/iasCynd/fD6C2a3LDUhXl6H8TYxwU/iJkb3qH3gcz1own7wHZPFy6dNXfeVVaFTn gu7zkK10H+OZesOgdX0botIF+JOpy65Udmev9oD+p1RrlojflHwgBLIPq0gEuiWF1zRW Sp9sxqfhm934n6MHBcvclRzKD2S/uQnNrwMRjVG1MM9QyFDynfqCfy95BVVLUpDESmQL EGkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716726407; x=1717331207; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KxtsOOjIQD+5fdn20u7+8eRQWnzhtvstNVtvMn8QGkc=; b=tul5QuSZbCbRKGUtphYW3r6sWemjG0dVEPrxR4sr2tNsSXOti1m2PDqEbSwCo1s4GR c4skTUxZVxkjgiNaf38XVqN2I31GBAuIdnHxrRgNM+AMFe/9xtrgpSZU9KNYHft6z10g ItkhX7jL17SpmxkouN29hLbCUXf4UoWmBqh8eU0exNAax6uIFkIBixh3Nclj76TQSIWf FR8JSDFtfIzOJJNd43fdUlO1uGueXad1m0QAJUtstMsmT/PM3QdUlHPSSh8nkokvE8JF XP1/RNOWkOWJ+ZAga2wkuGT6wsOEZfiwNwcHH9zBrcd8uwy7ZzjI8AlEiOWg1aW2G9Ey wqZg== X-Forwarded-Encrypted: i=1; AJvYcCXvtLWRwKC/w86Xnx0y8oKuOxS0W5+8fYHlsgpHkiPUXRfcQMDrVaEzvj+ZcAE+lQ98B9WSjusCDmbMPAEqV31q6Czkk0k= X-Gm-Message-State: AOJu0YyP4s1HFJ8Ij7QcplcaMha0lT3SiQDNVlJ15iI4D3sbda+5IZF9 CHIg3GKRbTtzJBxDE2PNgQIouSoMoORdUpL84KSwExf+DHP+FAVqiP7bFQ== X-Google-Smtp-Source: AGHT+IHFjBjLzfw+yubnSNh/oHL6cKhmHOVf8i706brp/H6k9T82RdeAN8DJv+fnFdpQVQNOWDYLlg== X-Received: by 2002:a05:6a21:1518:b0:1b1:d591:d24 with SMTP id adf61e73a8af0-1b212d2a8f5mr7664391637.16.1716726407375; Sun, 26 May 2024 05:26:47 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Caleb Schlossin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Daniel Henrique Barboza , qemu-devel@nongnu.org Subject: [RFC PATCH 07/10] target/ppc: Add helpers to check for SMT sibling threads Date: Sun, 26 May 2024 22:26:08 +1000 Message-ID: <20240526122612.473476-8-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240526122612.473476-1-npiggin@gmail.com> References: <20240526122612.473476-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=npiggin@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1716726446253100001 Content-Type: text/plain; charset="utf-8" Add helpers for TCG code to determine if there are SMT siblings sharing per-core and per-lpar registers. This simplifies the callers and makes SMT register topology simpler to modify with later changes. Signed-off-by: Nicholas Piggin Reviewed-by: Harsh Prateek Bora --- target/ppc/cpu.h | 7 +++++++ target/ppc/cpu_init.c | 2 +- target/ppc/excp_helper.c | 16 +++++++--------- target/ppc/misc_helper.c | 27 ++++++--------------------- target/ppc/timebase_helper.c | 20 +++++++------------- 5 files changed, 28 insertions(+), 44 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 9a89083932..8fd6ade471 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1406,6 +1406,13 @@ struct CPUArchState { uint64_t pmu_base_time; }; =20 +#define PPC_CPU_HAS_CORE_SIBLINGS(cs) \ + (cs->nr_threads > 1) + +#define PPC_CPU_HAS_LPAR_SIBLINGS(cs) \ + ((POWERPC_CPU(cs)->env.flags & POWERPC_FLAG_SMT_1LPAR) && \ + PPC_CPU_HAS_CORE_SIBLINGS(cs)) + #define _CORE_ID(cs) \ (POWERPC_CPU(cs)->env.core_index) =20 diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index ae483e20c4..e71ee008ed 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6975,7 +6975,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error *= *errp) =20 pcc->parent_realize(dev, errp); =20 - if (env_cpu(env)->nr_threads > 1) { + if (PPC_CPU_HAS_CORE_SIBLINGS(cs)) { env->flags |=3D POWERPC_FLAG_SMT; } =20 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0cd542675f..fd45da0f2b 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3029,7 +3029,7 @@ void helper_book3s_msgsnd(CPUPPCState *env, target_ul= ong rb) brdcast =3D true; } =20 - if (cs->nr_threads =3D=3D 1 || !brdcast) { + if (!PPC_CPU_HAS_CORE_SIBLINGS(cs) || !brdcast) { ppc_set_irq(cpu, PPC_INTERRUPT_HDOORBELL, 1); return; } @@ -3067,21 +3067,19 @@ void helper_book3s_msgsndp(CPUPPCState *env, target= _ulong rb) CPUState *cs =3D env_cpu(env); PowerPCCPU *cpu =3D env_archcpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; int ttir =3D rb & PPC_BITMASK(57, 63); =20 helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP); =20 - if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { - nr_threads =3D 1; /* msgsndp behaves as 1-thread in LPAR-per-threa= d mode*/ - } - - if (!dbell_type_server(rb) || ttir >=3D nr_threads) { + if (!dbell_type_server(rb)) { return; } =20 - if (nr_threads =3D=3D 1) { - ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, 1); + /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/ + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { + if (ttir =3D=3D 0) { + ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, 1); + } return; } =20 diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 46ba3a5584..598c956cdd 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -49,9 +49,8 @@ void helper_spr_core_write_generic(CPUPPCState *env, uint= 32_t sprn, { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1) { + if (!PPC_CPU_HAS_CORE_SIBLINGS(cs)) { env->spr[sprn] =3D val; return; } @@ -196,7 +195,7 @@ void helper_store_ptcr(CPUPPCState *env, target_ulong v= al) return; } =20 - if (cs->nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LP= AR)) { + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { env->spr[SPR_PTCR] =3D val; tlb_flush(cs); } else { @@ -243,16 +242,12 @@ target_ulong helper_load_dpdes(CPUPPCState *env) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; target_ulong dpdes =3D 0; =20 helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MS= GP); =20 - if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { - nr_threads =3D 1; /* DPDES behaves as 1-thread in LPAR-per-thread = mode */ - } - - if (nr_threads =3D=3D 1) { + /* DPDES behaves as 1-thread in LPAR-per-thread mode */ + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { dpdes =3D 1; } @@ -279,21 +274,11 @@ void helper_store_dpdes(CPUPPCState *env, target_ulon= g val) PowerPCCPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_M= SGP); =20 - if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) { - nr_threads =3D 1; /* DPDES behaves as 1-thread in LPAR-per-thread = mode */ - } - - if (val & ~(nr_threads - 1)) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value " - TARGET_FMT_lx"\n", val); - val &=3D (nr_threads - 1); /* Ignore the invalid bits */ - } - - if (nr_threads =3D=3D 1) { + /* DPDES behaves as 1-thread in LPAR-per-thread mode */ + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1); return; } diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 788c498d63..abe7b95696 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -63,9 +63,8 @@ void helper_store_purr(CPUPPCState *env, target_ulong val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { cpu_ppc_store_purr(env, val); return; } @@ -82,9 +81,8 @@ void helper_store_tbl(CPUPPCState *env, target_ulong val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { cpu_ppc_store_tbl(env, val); return; } @@ -99,9 +97,8 @@ void helper_store_tbu(CPUPPCState *env, target_ulong val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { cpu_ppc_store_tbu(env, val); return; } @@ -141,9 +138,8 @@ void helper_store_hdecr(CPUPPCState *env, target_ulong = val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { cpu_ppc_store_hdecr(env, val); return; } @@ -158,9 +154,8 @@ void helper_store_vtb(CPUPPCState *env, target_ulong va= l) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { cpu_ppc_store_vtb(env, val); return; } @@ -175,9 +170,8 @@ void helper_store_tbu40(CPUPPCState *env, target_ulong = val) { CPUState *cs =3D env_cpu(env); CPUState *ccs; - uint32_t nr_threads =3D cs->nr_threads; =20 - if (nr_threads =3D=3D 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) { cpu_ppc_store_tbu40(env, val); return; } @@ -288,7 +282,7 @@ static void write_tfmr(CPUPPCState *env, target_ulong v= al) { CPUState *cs =3D env_cpu(env); =20 - if (cs->nr_threads =3D=3D 1) { + if (!PPC_CPU_HAS_CORE_SIBLINGS(cs)) { env->spr[SPR_TFMR] =3D val; } else { CPUState *ccs; --=20 2.43.0