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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fcfe648bsm3457182b3a.168.2024.05.26.05.26.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 05:26:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716726403; x=1717331203; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8HcYPwV6XCSqjrlNZ2r5bJKShIDF7V+jrAWQcaF5Fd4=; b=VtuNZb1hfPMfe+wrXCiiCVkWVgLOvAnSwRUfQSvLiLyRXA+od5Rg4Clfc7tn6WcxCa /2FHz+TMedmc3FYv1N2/FvLHB08iAythooU1pjiwn3KG9m1AhP7K3bIq0sgFyzxmcaqA g9MnPacKr8H08bVLn3aAHNIjdEz6NWTkvuF4NqJVqeVC3Xh+wFuQReWP5avTZTVxMFKr 045aEHtcDA5ThgSwSJQvstG2HGXNsm77gecaEDcWnVD8fD5QXUd2QxLI9u7qBiGIgclu jejcl44SYVjJHlwuWnvEBYUpAVMmvOwVbXfZQRR3SW72GihhvTaCgNKwB+HS/kZe9KUO Gc8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716726403; x=1717331203; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8HcYPwV6XCSqjrlNZ2r5bJKShIDF7V+jrAWQcaF5Fd4=; b=lZEVH9qp2qZNJdFwCOfycSR/3GKfgHGdCf3TGC5Ht9rpF2Mc2QlTSDHmvNNWSdzH8F y3IKFw/M19mxsBvCbrr8WiupBfJooVkWTjURn27ybaJ4645ypBYPM4veJQKqja2OYHnd gBXpnnB0uLYrcy20T56CusFf+iLTH5p1ZgNonYiE+ExDfOUAI0JBZqU7V3UN4LsKNxb6 Uo2if/pKaknk0hKmTB7G9fVncksqq5rD+JnYlHQnctHXkOnkNa+dagJwodVWQVrMfilf C+tPRqaW21zgTz9N5M/saLTGC4gkIMUadcuVr4/NSP/xf7sp6YzXh9jBhCsb4qwm/MuB LbBw== X-Forwarded-Encrypted: i=1; AJvYcCWDS9KPvroHg3Fu2E6EcTtjKHqqsVWf/RLhRuMj/xl4p0KloqqDVLjLNI7YjEtuKrpkC+sb+D84INLVtQK5UhDO0na3NJc= X-Gm-Message-State: AOJu0Yz18exY5yDhJgWXgcgou6pfKi9fdkNgSXyufr04inbjMNnePkRu fpEXH+r9cvw6GZKLxEcOMNfcCVeVWTgHD+IMbP6m4/++AuscRXMJfcdy5Q== X-Google-Smtp-Source: AGHT+IGiCxQZVmeHAC0Oh8hcu8HqDjj+JnXyTz1UmwHwIzZoeCsVLDQw12ePDL+gOux36QvJ6KwMeQ== X-Received: by 2002:a05:6a00:4093:b0:6e6:9f47:c18c with SMTP id d2e1a72fcca58-6f8f41a9f2dmr6694534b3a.33.1716726403357; Sun, 26 May 2024 05:26:43 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Caleb Schlossin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Daniel Henrique Barboza , qemu-devel@nongnu.org Subject: [RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs Date: Sun, 26 May 2024 22:26:07 +1000 Message-ID: <20240526122612.473476-7-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240526122612.473476-1-npiggin@gmail.com> References: <20240526122612.473476-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=npiggin@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1716726436344100003 Content-Type: text/plain; charset="utf-8" The way SMT thread siblings are matched is clunky, using hard-coded logic that checks the PIR SPR. Change that to use a new core_index variable in the CPUPPCState, where all siblings have the same core_index. CPU realize routines have flexibility in setting core/sibling topology. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 5 ++++- hw/ppc/pnv_core.c | 2 ++ hw/ppc/spapr_cpu_core.c | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index dac13d4dac..9a89083932 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1247,6 +1247,9 @@ struct CPUArchState { /* when a memory exception occurs, the access type is stored here */ int access_type; =20 + /* For SMT processors */ + int core_index; + #if !defined(CONFIG_USER_ONLY) /* MMU context, only relevant for full system emulation */ #if defined(TARGET_PPC64) @@ -1404,7 +1407,7 @@ struct CPUArchState { }; =20 #define _CORE_ID(cs) \ - (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads= - 1)) + (POWERPC_CPU(cs)->env.core_index) =20 #define THREAD_SIBLING_FOREACH(cs, cs_sibling) \ CPU_FOREACH(cs_sibling) \ diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 9b5edd9e48..0f61aabb77 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -252,6 +252,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCP= U *cpu, Error **errp, pir_spr->default_value =3D pir; tir_spr->default_value =3D tir; =20 + env->core_index =3D core_hwid; + /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index e7c9edd033..059d372c8a 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -300,16 +300,19 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc= , int i, Error **errp) g_autofree char *id =3D NULL; CPUState *cs; PowerPCCPU *cpu; + CPUPPCState *env; =20 obj =3D object_new(scc->cpu_type); =20 cs =3D CPU(obj); cpu =3D POWERPC_CPU(obj); + env =3D &cpu->env; /* * All CPUs start halted. CPU0 is unhalted from the machine level rese= t code * and the rest are explicitly started up by the guest using an RTAS c= all. */ qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); + env->core_index =3D cc->core_id; cs->cpu_index =3D cc->core_id + i; if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) { return NULL; --=20 2.43.0