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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fcfe648bsm3457182b3a.168.2024.05.26.05.26.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 05:26:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716726399; x=1717331199; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qaa1CJNZBddwryvQGk2blXK8TkhlUvCCGTcuF5Y8qHE=; b=N72bm8eJ1QicayRbRR17N+/XrP8TXrm+X7oTzq+/lwBCOjrRWDPlF030zogWuk+Oh3 uoobrocubhPdegCrvqA8L+Gr+FwcRezkgC4/Mdgat+1Mv3DgO6YPOD1Va0Sy7t3dPPL7 K++C+ufaooh5eyjds1RvWV+sP3ao9tG+S9QLdnZ1Aqi8mgQbBvcYpAPymLdltsGoRocU i+iHMpVHe+KolWe1oZljTZ/QvU/XNTABD3XN4Olu8c5UnqZmWV5iu9C1HWfrJOVL5zTU TWkvsRn9hpBwpIWiNf4dA4bt7k6YeNZasUL3WMZExnNryH8c4D+Z46HX+kx8Movil39V bLfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716726399; x=1717331199; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qaa1CJNZBddwryvQGk2blXK8TkhlUvCCGTcuF5Y8qHE=; b=AJlZp7oahb+/32bT2/XrqJ6ehRWWwsgINphxJYy4PPacLLAzKgERCclZ4LGZMMCHdN DlqHdW70z2zSAQR13AJHBPa1BuYNkw4bvE10+KNAO+EbpXwyGbZSp2CZRI179pUczPQp 6w2k2wvY/XLKcs/yjB/1ekwmpz5hWgUUNvquS2hLMdM8iA7IkfzO8FaHlxj+61Y8JptZ sPzi6E9F1XnEE+DDD0hwSN9EBqDybO7peb2zdNcW7CDz19WWuCa6aX4wTCAV+SwERPfi 3my1phcgUOrZKuzSviQ+ytnqrPlm74DRA26nsAbh8hQuW0Vs2WHXiF0ZUWScsV0/YW0T 6E5g== X-Forwarded-Encrypted: i=1; AJvYcCUDPOQu9dCsYE/uz55htxKhQTjpb098y8Xsp2u/2YkkfMBY9l0IDBzF3LpBMEsZm/EStq+eaqO2PA+gN4u05S1GKq973P8= X-Gm-Message-State: AOJu0YyTEZMOLlDE67s49sEejaPMIcG78YM/OvtxUT03Oz1rGPQL8ani ZLBZ/Mrf7Sd+AGuKFmRukh8W8fJpn5xQqz0iKOplorEjfHa6bpI64jnlWw== X-Google-Smtp-Source: AGHT+IG07y+vZ4y0eyZICzLbhhBq+op1D5zAMbEM2+NtNNNX1DvXXhdCb3sEYW41PVDgAv2rQMUe4w== X-Received: by 2002:a92:cda6:0:b0:36d:b4b0:9c8e with SMTP id e9e14a558f8ab-3737b2f0d8bmr74180845ab.8.1716726399561; Sun, 26 May 2024 05:26:39 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Caleb Schlossin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Daniel Henrique Barboza , qemu-devel@nongnu.org Subject: [RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well Date: Sun, 26 May 2024 22:26:06 +1000 Message-ID: <20240526122612.473476-6-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240526122612.473476-1-npiggin@gmail.com> References: <20240526122612.473476-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::135; envelope-from=npiggin@gmail.com; helo=mail-il1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1716726518552100011 Content-Type: text/plain; charset="utf-8" The chip_pir chip class method allows the platform to set the PIR processor identification register. Extend this to a more general ID function which also allows the TIR to be set. This is in preparation for "big core", which is a more complicated topology of cores and threads. Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_chip.h | 3 +- hw/ppc/pnv.c | 61 ++++++++++++++++++++++++--------------- hw/ppc/pnv_core.c | 10 ++++--- 3 files changed, 45 insertions(+), 29 deletions(-) diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 8589f3291e..679723926a 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -147,7 +147,8 @@ struct PnvChipClass { =20 DeviceRealize parent_realize; =20 - uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_= id); + void (*processor_id)(PnvChip *chip, uint32_t core_id, uint32_t thread_= id, + uint32_t *pir, uint32_t *tir); void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index a706de2e36..7d062ec16c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -144,7 +144,7 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void= *fdt) PnvChipClass *pnv_cc =3D PNV_CHIP_GET_CLASS(chip); g_autofree uint32_t *servers_prop =3D g_new(uint32_t, smt_threads); int i; - uint32_t pir; + uint32_t pir, tir; uint32_t segs[] =3D {cpu_to_be32(28), cpu_to_be32(40), 0xffffffff, 0xffffffff}; uint32_t tbfreq =3D PNV_TIMEBASE_FREQ; @@ -155,7 +155,7 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void= *fdt) char *nodename; int cpus_offset =3D get_cpus_node(fdt); =20 - pir =3D pnv_cc->chip_pir(chip, pc->hwid, 0); + pnv_cc->processor_id(chip, pc->hwid, 0, &pir, &tir); =20 nodename =3D g_strdup_printf("%s@%x", dc->fw_name, pir); offset =3D fdt_add_subnode(fdt, cpus_offset, nodename); @@ -237,7 +237,8 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void= *fdt) =20 /* Build interrupt servers properties */ for (i =3D 0; i < smt_threads; i++) { - servers_prop[i] =3D cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i= )); + pnv_cc->processor_id(chip, pc->hwid, i, &pir, &tir); + servers_prop[i] =3D cpu_to_be32(pir); } _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", servers_prop, sizeof(*servers_prop) * smt_threads))= ); @@ -249,14 +250,17 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint= 32_t hwid, uint32_t nr_threads) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - uint32_t pir =3D pcc->chip_pir(chip, hwid, 0); - uint64_t addr =3D PNV_ICP_BASE(chip) | (pir << 12); + uint32_t pir, tir; + uint64_t addr; char *name; const char compat[] =3D "IBM,power8-icp\0IBM,ppc-xicp"; uint32_t irange[2], i, rsize; uint64_t *reg; int offset; =20 + pcc->processor_id(chip, hwid, 0, &pir, &tir); + addr =3D PNV_ICP_BASE(chip) | (pir << 12); + irange[0] =3D cpu_to_be32(pir); irange[1] =3D cpu_to_be32(nr_threads); =20 @@ -1104,10 +1108,12 @@ static void pnv_power10_init(MachineState *machine) * 25:28 Core number * 29:31 Thread ID */ -static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, - uint32_t thread_id) +static void pnv_processor_id_p8(PnvChip *chip, + uint32_t core_id, uint32_t thread_id, + uint32_t *pir, uint32_t *tir) { - return (chip->chip_id << 7) | (core_id << 3) | thread_id; + *pir =3D (chip->chip_id << 7) | (core_id << 3) | thread_id; + *tir =3D thread_id; } =20 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, @@ -1159,15 +1165,17 @@ static void pnv_chip_power8_intc_print_info(PnvChip= *chip, PowerPCCPU *cpu, * * We only care about the lower bits. uint32_t is fine for the moment. */ -static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, - uint32_t thread_id) +static void pnv_processor_id_p9(PnvChip *chip, + uint32_t core_id, uint32_t thread_id, + uint32_t *pir, uint32_t *tir) { if (chip->nr_threads =3D=3D 8) { - return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id <<= 3) | + *pir =3D (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id = << 3) | (thread_id >> 1); } else { - return (chip->chip_id << 8) | (core_id << 2) | thread_id; + *pir =3D (chip->chip_id << 8) | (core_id << 2) | thread_id; } + *tir =3D thread_id; } =20 /* @@ -1181,15 +1189,17 @@ static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint= 32_t core_id, * * We only care about the lower bits. uint32_t is fine for the moment. */ -static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, - uint32_t thread_id) +static void pnv_processor_id_p10(PnvChip *chip, + uint32_t core_id, uint32_t thread_id, + uint32_t *pir, uint32_t *tir) { if (chip->nr_threads =3D=3D 8) { - return (chip->chip_id << 8) | ((core_id / 4) << 4) | - ((core_id % 2) << 3) | thread_id; + *pir =3D (chip->chip_id << 8) | ((core_id / 4) << 4) | + ((core_id % 2) << 3) | thread_id; } else { - return (chip->chip_id << 8) | (core_id << 2) | thread_id; + *pir =3D (chip->chip_id << 8) | (core_id << 2) | thread_id; } + *tir =3D thread_id; } =20 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, @@ -1368,8 +1378,11 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Er= ror **errp) int core_hwid =3D CPU_CORE(pnv_core)->core_id; =20 for (j =3D 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { - uint32_t pir =3D pcc->chip_pir(chip, core_hwid, j); - PnvICPState *icp =3D PNV_ICP(xics_icp_get(chip8->xics, pir)); + uint32_t pir, tir; + PnvICPState *icp; + + pcc->processor_id(chip, core_hwid, j, &pir, &tir); + icp =3D PNV_ICP(xics_icp_get(chip8->xics, pir)); =20 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, &icp->mmio); @@ -1481,7 +1494,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; k->num_phbs =3D 3; - k->chip_pir =3D pnv_chip_pir_p8; + k->processor_id =3D pnv_processor_id_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; @@ -1505,7 +1518,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->num_phbs =3D 3; - k->chip_pir =3D pnv_chip_pir_p8; + k->processor_id =3D pnv_processor_id_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; @@ -1529,7 +1542,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->num_phbs =3D 4; - k->chip_pir =3D pnv_chip_pir_p8; + k->processor_id =3D pnv_processor_id_p8; k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; @@ -1802,7 +1815,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) =20 k->chip_cfam_id =3D 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ k->cores_mask =3D POWER9_CORE_MASK; - k->chip_pir =3D pnv_chip_pir_p9; + k->processor_id =3D pnv_processor_id_p9; k->intc_create =3D pnv_chip_power9_intc_create; k->intc_reset =3D pnv_chip_power9_intc_reset; k->intc_destroy =3D pnv_chip_power9_intc_destroy; @@ -2114,7 +2127,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) =20 k->chip_cfam_id =3D 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ k->cores_mask =3D POWER10_CORE_MASK; - k->chip_pir =3D pnv_chip_pir_p10; + k->processor_id =3D pnv_processor_id_p10; k->intc_create =3D pnv_chip_power10_intc_create; k->intc_reset =3D pnv_chip_power10_intc_reset; k->intc_destroy =3D pnv_chip_power10_intc_destroy; diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 7b0ea7812b..9b5edd9e48 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -228,8 +228,9 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCP= U *cpu, Error **errp, PnvCPUState *pnv_cpu =3D pnv_cpu_state(cpu); CPUPPCState *env =3D &cpu->env; int core_hwid; - ppc_spr_t *pir =3D &env->spr_cb[SPR_PIR]; - ppc_spr_t *tir =3D &env->spr_cb[SPR_TIR]; + ppc_spr_t *pir_spr =3D &env->spr_cb[SPR_PIR]; + ppc_spr_t *tir_spr =3D &env->spr_cb[SPR_TIR]; + uint32_t pir, tir; Error *local_err =3D NULL; PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(pc->chip); =20 @@ -247,8 +248,9 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCP= U *cpu, Error **errp, =20 core_hwid =3D object_property_get_uint(OBJECT(pc), "hwid", &error_abor= t); =20 - tir->default_value =3D thread_index; - pir->default_value =3D pcc->chip_pir(pc->chip, core_hwid, thread_index= ); + pcc->processor_id(pc->chip, core_hwid, thread_index, &pir, &tir); + pir_spr->default_value =3D pir; + tir_spr->default_value =3D tir; =20 /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); --=20 2.43.0