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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c759ceesm19178305ad.10.2024.05.24.16.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 16:21:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716592901; x=1717197701; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H2xFCppnIKFVialQo7UwJzgtJAAgE8nOt0WWcTAkceY=; b=gypTIJB68epyoYNrlrB18NUvsUl+V/DfYWda8p+nzYMjg1Rlm1dXKZsUm6r5riPG4s 5UHyKzMrCBh2UNYdWwuGRjVL9zT4E74lBW/9LwzLp9UntgFG+GVQ09nt9f2GWPA9i6qr 32PIuJpvhAbxhypmtWJLIi7OhaCXRzRntAUb0hNi7Hq9Is8fhzO3ygqIXzArthRZc1Ah ZD07f00gS+aknSg21gbvqc/So5pQ0VVM61EGNiLAQ0jVw1wRbwvtMGgbY4l9ThDVjae1 O3Fl5vF9PPU0KQZle5RpT6kDbW8IGlOG/lqJml8/rEeFi/KPw3dumDSg6YhQphcazrKD qmXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716592901; x=1717197701; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H2xFCppnIKFVialQo7UwJzgtJAAgE8nOt0WWcTAkceY=; b=BGtVFOIgMXoApLrfgB6Jg6KsS5UMejK1PuoQTftMWU/WmlAmUkxLRRr5xl3enrkZ0O KXgg6L2+1ni3CT08+D5QO12LX5WlMPDNcaiXSKhI+asGBV7ncimgzjiTO1iOiS0hRQUF U3qlHAuB1lbvKV7g8xtNI4ZQacEV+EI1JKlei+C/NK62PmcFHK8O5n9Z8hqfbS7qyP03 YNdG2ylK0qO4vWsNzUoW2qzLbvW7POl/pGlzvgm648fvBcfniMU8FIo49F5fFTFGKNeT Jckvj1XiaiKtW4vc7VOUKDljMTekYZgzAoDFhHuKVRuno/BKPF7/bC44K8cr2kHxaVn5 qRmw== X-Gm-Message-State: AOJu0Yz8YI3M9luWRJtEAvpgTVxhmvD/ySFaxg+Ae960kN6c0XvROw62 +8yTXLiF1kPQXNWQAe8YunCvtQNWSz2sU3eMoWB5jZVMLXqyRQbJ4+7PqGUm9q91ncr6VAnFV5i H X-Google-Smtp-Source: AGHT+IEUVQbtE+LbmuqaYkwk0mABelVPtxg6b32Rz8NKZ0x+edBJl4L8XrOYNrtT0uF0znPpRBAnmw== X-Received: by 2002:a17:902:eccd:b0:1e3:e39a:2e49 with SMTP id d9443c01a7336-1f4486da10bmr43862815ad.18.1716592901494; Fri, 24 May 2024 16:21:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 21/67] target/arm: Introduce vfp_load_reg16 Date: Fri, 24 May 2024 16:20:35 -0700 Message-Id: <20240524232121.284515-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240524232121.284515-1-richard.henderson@linaro.org> References: <20240524232121.284515-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716593401150100004 Content-Type: text/plain; charset="utf-8" Load and zero-extend float16 into a TCGv_i32 before all scalar operations. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/translate-vfp.c | 39 +++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index b9af03b7c3..8e755fcde8 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -48,6 +48,12 @@ static inline void vfp_store_reg32(TCGv_i32 var, int reg) tcg_gen_st_i32(var, tcg_env, vfp_reg_offset(false, reg)); } =20 +static inline void vfp_load_reg16(TCGv_i32 var, int reg) +{ + tcg_gen_ld16u_i32(var, tcg_env, + vfp_reg_offset(false, reg) + HOST_BIG_ENDIAN * 2); +} + /* * The imm8 encodes the sign bit, enough bits to represent an exponent in * the range 01....1xx to 10....0xx, and the most significant 4 bits of @@ -902,8 +908,7 @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_s= ingle *a) if (a->l) { /* VFP to general purpose register */ tmp =3D tcg_temp_new_i32(); - vfp_load_reg32(tmp, a->vn); - tcg_gen_andi_i32(tmp, tmp, 0xffff); + vfp_load_reg16(tmp, a->vn); store_reg(s, a->rt, tmp); } else { /* general purpose register to VFP */ @@ -1453,11 +1458,11 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3O= pSPFn *fn, fd =3D tcg_temp_new_i32(); fpst =3D fpstatus_ptr(FPST_FPCR_F16); =20 - vfp_load_reg32(f0, vn); - vfp_load_reg32(f1, vm); + vfp_load_reg16(f0, vn); + vfp_load_reg16(f1, vm); =20 if (reads_vd) { - vfp_load_reg32(fd, vd); + vfp_load_reg16(fd, vd); } fn(fd, f0, f1, fpst); vfp_store_reg32(fd, vd); @@ -1633,7 +1638,7 @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) } =20 f0 =3D tcg_temp_new_i32(); - vfp_load_reg32(f0, vm); + vfp_load_reg16(f0, vm); fn(f0, f0); vfp_store_reg32(f0, vd); =20 @@ -2106,13 +2111,13 @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp = *a, bool neg_n, bool neg_d) vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i32(); =20 - vfp_load_reg32(vn, a->vn); - vfp_load_reg32(vm, a->vm); + vfp_load_reg16(vn, a->vn); + vfp_load_reg16(vm, a->vm); if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negh(vn, vn); } - vfp_load_reg32(vd, a->vd); + vfp_load_reg16(vd, a->vd); if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negh(vd, vd); @@ -2456,11 +2461,11 @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP= _sp *a) vd =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i32(); =20 - vfp_load_reg32(vd, a->vd); + vfp_load_reg16(vd, a->vd); if (a->z) { tcg_gen_movi_i32(vm, 0); } else { - vfp_load_reg32(vm, a->vm); + vfp_load_reg16(vm, a->vm); } =20 if (a->e) { @@ -2700,7 +2705,7 @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRIN= TR_sp *a) } =20 tmp =3D tcg_temp_new_i32(); - vfp_load_reg32(tmp, a->vm); + vfp_load_reg16(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_rinth(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); @@ -2773,7 +2778,7 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRIN= TZ_sp *a) } =20 tmp =3D tcg_temp_new_i32(); - vfp_load_reg32(tmp, a->vm); + vfp_load_reg16(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR_F16); tcg_rmode =3D gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rinth(tmp, tmp, fpst); @@ -2853,7 +2858,7 @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRIN= TX_sp *a) } =20 tmp =3D tcg_temp_new_i32(); - vfp_load_reg32(tmp, a->vm); + vfp_load_reg16(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_rinth_exact(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); @@ -3270,7 +3275,7 @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VC= VT_sp_int *a) =20 fpst =3D fpstatus_ptr(FPST_FPCR_F16); vm =3D tcg_temp_new_i32(); - vfp_load_reg32(vm, a->vm); + vfp_load_reg16(vm, a->vm); =20 if (a->s) { if (a->rz) { @@ -3383,8 +3388,8 @@ static bool trans_VINS(DisasContext *s, arg_VINS *a) /* Insert low half of Vm into high half of Vd */ rm =3D tcg_temp_new_i32(); rd =3D tcg_temp_new_i32(); - vfp_load_reg32(rm, a->vm); - vfp_load_reg32(rd, a->vd); + vfp_load_reg16(rm, a->vm); + vfp_load_reg16(rd, a->vd); tcg_gen_deposit_i32(rd, rd, rm, 16, 16); vfp_store_reg32(rd, a->vd); return true; --=20 2.34.1