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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=porter@cs.unc.edu; helo=mail-qk1-x72a.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @cs.unc.edu) X-ZM-MESSAGEID: 1716570601377100012 Content-Type: text/plain; charset="utf-8" Signed-off-by: Don Porter --- target/i386/arch_memory_mapping.c | 318 ++++-------------------------- 1 file changed, 40 insertions(+), 278 deletions(-) diff --git a/target/i386/arch_memory_mapping.c b/target/i386/arch_memory_ma= pping.c index 00bf2a2116..040464dd34 100644 --- a/target/i386/arch_memory_mapping.c +++ b/target/i386/arch_memory_mapping.c @@ -19,6 +19,7 @@ ************** code hook implementations for x86 *********** */ =20 +/* PAE Paging or IA-32e Paging */ #define PML4_ADDR_MASK 0xffffffffff000ULL /* selects bits 51:12 */ =20 /** @@ -499,302 +500,63 @@ bool for_each_pte(CPUState *cs, /** * Back to x86 hooks */ +struct memory_mapping_data { + MemoryMappingList *list; +}; =20 -/* PAE Paging or IA-32e Paging */ -static void walk_pte(MemoryMappingList *list, AddressSpace *as, - hwaddr pte_start_addr, - int32_t a20_mask, target_ulong start_line_addr) -{ - hwaddr pte_addr, start_paddr; - uint64_t pte; - target_ulong start_vaddr; - int i; - - for (i =3D 0; i < 512; i++) { - pte_addr =3D (pte_start_addr + i * 8) & a20_mask; - pte =3D address_space_ldq(as, pte_addr, MEMTXATTRS_UNSPECIFIED, NU= LL); - if (!(pte & PG_PRESENT_MASK)) { - /* not present */ - continue; - } - - start_paddr =3D (pte & ~0xfff) & ~(0x1ULL << 63); - if (cpu_physical_memory_is_io(start_paddr)) { - /* I/O region */ - continue; - } - - start_vaddr =3D start_line_addr | ((i & 0x1ff) << 12); - memory_mapping_list_add_merge_sorted(list, start_paddr, - start_vaddr, 1 << 12); - } -} - -/* 32-bit Paging */ -static void walk_pte2(MemoryMappingList *list, AddressSpace *as, - hwaddr pte_start_addr, int32_t a20_mask, - target_ulong start_line_addr) -{ - hwaddr pte_addr, start_paddr; - uint32_t pte; - target_ulong start_vaddr; - int i; - - for (i =3D 0; i < 1024; i++) { - pte_addr =3D (pte_start_addr + i * 4) & a20_mask; - pte =3D address_space_ldl(as, pte_addr, MEMTXATTRS_UNSPECIFIED, NU= LL); - if (!(pte & PG_PRESENT_MASK)) { - /* not present */ - continue; - } - - start_paddr =3D pte & ~0xfff; - if (cpu_physical_memory_is_io(start_paddr)) { - /* I/O region */ - continue; - } - - start_vaddr =3D start_line_addr | ((i & 0x3ff) << 12); - memory_mapping_list_add_merge_sorted(list, start_paddr, - start_vaddr, 1 << 12); - } -} - -/* PAE Paging or IA-32e Paging */ -#define PLM4_ADDR_MASK 0xffffffffff000ULL /* selects bits 51:12 */ - -static void walk_pde(MemoryMappingList *list, AddressSpace *as, - hwaddr pde_start_addr, - int32_t a20_mask, target_ulong start_line_addr) +static int add_memory_mapping_to_list(CPUState *cs, void *data, PTE_t *pte, + target_ulong vaddr, int height, + int offset) { - hwaddr pde_addr, pte_start_addr, start_paddr; - uint64_t pde; - target_ulong line_addr, start_vaddr; - int i; - - for (i =3D 0; i < 512; i++) { - pde_addr =3D (pde_start_addr + i * 8) & a20_mask; - pde =3D address_space_ldq(as, pde_addr, MEMTXATTRS_UNSPECIFIED, NU= LL); - if (!(pde & PG_PRESENT_MASK)) { - /* not present */ - continue; - } - - line_addr =3D start_line_addr | ((i & 0x1ff) << 21); - if (pde & PG_PSE_MASK) { - /* 2 MB page */ - start_paddr =3D (pde & ~0x1fffff) & ~(0x1ULL << 63); - if (cpu_physical_memory_is_io(start_paddr)) { - /* I/O region */ - continue; - } - start_vaddr =3D line_addr; - memory_mapping_list_add_merge_sorted(list, start_paddr, - start_vaddr, 1 << 21); - continue; - } - - pte_start_addr =3D (pde & PLM4_ADDR_MASK) & a20_mask; - walk_pte(list, as, pte_start_addr, a20_mask, line_addr); - } -} + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; =20 -/* 32-bit Paging */ -static void walk_pde2(MemoryMappingList *list, AddressSpace *as, - hwaddr pde_start_addr, int32_t a20_mask, - bool pse) -{ - hwaddr pde_addr, pte_start_addr, start_paddr, high_paddr; - uint32_t pde; - target_ulong line_addr, start_vaddr; - int i; + struct memory_mapping_data *mm_data =3D (struct memory_mapping_data *)= data; =20 - for (i =3D 0; i < 1024; i++) { - pde_addr =3D (pde_start_addr + i * 4) & a20_mask; - pde =3D address_space_ldl(as, pde_addr, MEMTXATTRS_UNSPECIFIED, NU= LL); - if (!(pde & PG_PRESENT_MASK)) { - /* not present */ - continue; + hwaddr start_paddr =3D 0; + size_t pg_size =3D mmu_pte_leaf_page_size(cs, height); + switch (height) { + case 1: + start_paddr =3D pte->pte64_t & ~0xfff; + if (env->cr[4] & CR4_PAE_MASK) { + start_paddr &=3D ~(0x1ULL << 63); } - - line_addr =3D (((unsigned int)i & 0x3ff) << 22); - if ((pde & PG_PSE_MASK) && pse) { + break; + case 2: + if (env->cr[4] & CR4_PAE_MASK) { + start_paddr =3D (pte->pte64_t & ~0x1fffff) & ~(0x1ULL << 63); + } else { + assert(!!(env->cr[4] & CR4_PSE_MASK)); /* * 4 MB page: * bits 39:32 are bits 20:13 of the PDE * bit3 31:22 are bits 31:22 of the PDE */ - high_paddr =3D ((hwaddr)(pde & 0x1fe000) << 19); - start_paddr =3D (pde & ~0x3fffff) | high_paddr; - if (cpu_physical_memory_is_io(start_paddr)) { - /* I/O region */ - continue; - } - start_vaddr =3D line_addr; - memory_mapping_list_add_merge_sorted(list, start_paddr, - start_vaddr, 1 << 22); - continue; - } - - pte_start_addr =3D (pde & ~0xfff) & a20_mask; - walk_pte2(list, as, pte_start_addr, a20_mask, line_addr); - } -} - -/* PAE Paging */ -static void walk_pdpe2(MemoryMappingList *list, AddressSpace *as, - hwaddr pdpe_start_addr, int32_t a20_mask) -{ - hwaddr pdpe_addr, pde_start_addr; - uint64_t pdpe; - target_ulong line_addr; - int i; - - for (i =3D 0; i < 4; i++) { - pdpe_addr =3D (pdpe_start_addr + i * 8) & a20_mask; - pdpe =3D address_space_ldq(as, pdpe_addr, MEMTXATTRS_UNSPECIFIED, = NULL); - if (!(pdpe & PG_PRESENT_MASK)) { - /* not present */ - continue; + hwaddr high_paddr =3D ((hwaddr)(pte->pte64_t & 0x1fe000) << 19= ); + start_paddr =3D (pte->pte64_t & ~0x3fffff) | high_paddr; } - - line_addr =3D (((unsigned int)i & 0x3) << 30); - pde_start_addr =3D (pdpe & ~0xfff) & a20_mask; - walk_pde(list, as, pde_start_addr, a20_mask, line_addr); - } -} - -#ifdef TARGET_X86_64 -/* IA-32e Paging */ -static void walk_pdpe(MemoryMappingList *list, AddressSpace *as, - hwaddr pdpe_start_addr, int32_t a20_mask, - target_ulong start_line_addr) -{ - hwaddr pdpe_addr, pde_start_addr, start_paddr; - uint64_t pdpe; - target_ulong line_addr, start_vaddr; - int i; - - for (i =3D 0; i < 512; i++) { - pdpe_addr =3D (pdpe_start_addr + i * 8) & a20_mask; - pdpe =3D address_space_ldq(as, pdpe_addr, MEMTXATTRS_UNSPECIFIED, = NULL); - if (!(pdpe & PG_PRESENT_MASK)) { - /* not present */ - continue; - } - - line_addr =3D start_line_addr | ((i & 0x1ffULL) << 30); - if (pdpe & PG_PSE_MASK) { - /* 1 GB page */ - start_paddr =3D (pdpe & ~0x3fffffff) & ~(0x1ULL << 63); - if (cpu_physical_memory_is_io(start_paddr)) { - /* I/O region */ - continue; - } - start_vaddr =3D line_addr; - memory_mapping_list_add_merge_sorted(list, start_paddr, - start_vaddr, 1 << 30); - continue; - } - - pde_start_addr =3D (pdpe & PLM4_ADDR_MASK) & a20_mask; - walk_pde(list, as, pde_start_addr, a20_mask, line_addr); + break; + case 3: + /* Select bits 30--51 */ + start_paddr =3D (pte->pte64_t & 0xfffffc0000000); + break; + default: + g_assert_not_reached(); } -} - -/* IA-32e Paging */ -static void walk_pml4e(MemoryMappingList *list, AddressSpace *as, - hwaddr pml4e_start_addr, int32_t a20_mask, - target_ulong start_line_addr) -{ - hwaddr pml4e_addr, pdpe_start_addr; - uint64_t pml4e; - target_ulong line_addr; - int i; =20 - for (i =3D 0; i < 512; i++) { - pml4e_addr =3D (pml4e_start_addr + i * 8) & a20_mask; - pml4e =3D address_space_ldq(as, pml4e_addr, MEMTXATTRS_UNSPECIFIED, - NULL); - if (!(pml4e & PG_PRESENT_MASK)) { - /* not present */ - continue; - } - - line_addr =3D start_line_addr | ((i & 0x1ffULL) << 39); - pdpe_start_addr =3D (pml4e & PLM4_ADDR_MASK) & a20_mask; - walk_pdpe(list, as, pdpe_start_addr, a20_mask, line_addr); + /* This hook skips mappings for the I/O region */ + if (cpu_physical_memory_is_io(start_paddr)) { + /* I/O region */ + return 0; } -} =20 -static void walk_pml5e(MemoryMappingList *list, AddressSpace *as, - hwaddr pml5e_start_addr, int32_t a20_mask) -{ - hwaddr pml5e_addr, pml4e_start_addr; - uint64_t pml5e; - target_ulong line_addr; - int i; - - for (i =3D 0; i < 512; i++) { - pml5e_addr =3D (pml5e_start_addr + i * 8) & a20_mask; - pml5e =3D address_space_ldq(as, pml5e_addr, MEMTXATTRS_UNSPECIFIED, - NULL); - if (!(pml5e & PG_PRESENT_MASK)) { - /* not present */ - continue; - } - - line_addr =3D (0x7fULL << 57) | ((i & 0x1ffULL) << 48); - pml4e_start_addr =3D (pml5e & PLM4_ADDR_MASK) & a20_mask; - walk_pml4e(list, as, pml4e_start_addr, a20_mask, line_addr); - } + memory_mapping_list_add_merge_sorted(mm_data->list, start_paddr, + vaddr, pg_size); + return 0; } -#endif =20 bool x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list, Error **errp) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int32_t a20_mask; - - if (!cpu_paging_enabled(cs)) { - /* paging is disabled */ - return true; - } - - a20_mask =3D x86_get_a20_mask(env); - if (env->cr[4] & CR4_PAE_MASK) { -#ifdef TARGET_X86_64 - if (env->hflags & HF_LMA_MASK) { - if (env->cr[4] & CR4_LA57_MASK) { - hwaddr pml5e_addr; - - pml5e_addr =3D (env->cr[3] & PLM4_ADDR_MASK) & a20_mask; - walk_pml5e(list, cs->as, pml5e_addr, a20_mask); - } else { - hwaddr pml4e_addr; - - pml4e_addr =3D (env->cr[3] & PLM4_ADDR_MASK) & a20_mask; - walk_pml4e(list, cs->as, pml4e_addr, a20_mask, - 0xffffULL << 48); - } - } else -#endif - { - hwaddr pdpe_addr; - - pdpe_addr =3D (env->cr[3] & ~0x1f) & a20_mask; - walk_pdpe2(list, cs->as, pdpe_addr, a20_mask); - } - } else { - hwaddr pde_addr; - bool pse; - - pde_addr =3D (env->cr[3] & ~0xfff) & a20_mask; - pse =3D !!(env->cr[4] & CR4_PSE_MASK); - walk_pde2(list, cs->as, pde_addr, a20_mask, pse); - } - - return true; + return for_each_pte(cs, &add_memory_mapping_to_list, list, false, fals= e); } --=20 2.34.1