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Fri, 24 May 2024 01:10:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEkLnYpCjlOoGTWiQNIpiIuXci86y7vSmMhwG5fLep1/NBQc1IUTST4kkrgoOwBsDmgq5TvdQ== X-Received: by 2002:a17:906:788:b0:a59:adf8:a6e1 with SMTP id a640c23a62f3a-a62651144f1mr90975766b.47.1716538237979; Fri, 24 May 2024 01:10:37 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 08/16] target/i386: reg in gen_ldst_modrm is always OR_TMP0 Date: Fri, 24 May 2024 10:10:11 +0200 Message-ID: <20240524081019.1141359-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240524081019.1141359-1-pbonzini@redhat.com> References: <20240524081019.1141359-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716538403306100007 Content-Type: text/plain; charset="utf-8" Values other than OR_TMP0 were only ever used by MOV and MOVNTI opcodes. Now that these have been converted to the new decoder, remove the argument. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/translate.c | 33 ++++++++++++--------------------- 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index c46385be060..b75d61a9141 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1821,10 +1821,9 @@ static void gen_add_A0_ds_seg(DisasContext *s) gen_lea_v_seg(s, s->aflag, s->A0, R_DS, s->override); } =20 -/* generate modrm memory load or store of 'reg'. TMP0 is used if reg =3D= =3D - OR_TMP0 */ +/* generate modrm memory load or store of 'reg'. */ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, - MemOp ot, int reg, int is_store) + MemOp ot, int is_store) { int mod, rm; =20 @@ -1832,24 +1831,16 @@ static void gen_ldst_modrm(CPUX86State *env, DisasC= ontext *s, int modrm, rm =3D (modrm & 7) | REX_B(s); if (mod =3D=3D 3) { if (is_store) { - if (reg !=3D OR_TMP0) - gen_op_mov_v_reg(s, ot, s->T0, reg); gen_op_mov_reg_v(s, ot, rm, s->T0); } else { gen_op_mov_v_reg(s, ot, s->T0, rm); - if (reg !=3D OR_TMP0) - gen_op_mov_reg_v(s, ot, reg, s->T0); } } else { gen_lea_modrm(env, s, modrm); if (is_store) { - if (reg !=3D OR_TMP0) - gen_op_mov_v_reg(s, ot, s->T0, reg); gen_op_st_v(s, ot, s->T0, s->A0); } else { gen_op_ld_v(s, ot, s->T0, s->A0); - if (reg !=3D OR_TMP0) - gen_op_mov_reg_v(s, ot, reg, s->T0); } } } @@ -3440,7 +3431,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) ot =3D dflag; modrm =3D x86_ldub_code(env, s); reg =3D ((modrm >> 3) & 7) | REX_R(s); - gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, ot, 0); gen_extu(ot, s->T0); =20 /* Note that lzcnt and tzcnt are in different extensions. */ @@ -3587,14 +3578,14 @@ static void disas_insn_old(DisasContext *s, CPUStat= e *cpu, int b) tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, ldt.selector)); ot =3D mod =3D=3D 3 ? dflag : MO_16; - gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, ot, 1); break; case 2: /* lldt */ if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, SVM_EXIT_LDTR_WRITE); - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, MO_16, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_lldt(tcg_env, s->tmp2_i32); } @@ -3609,14 +3600,14 @@ static void disas_insn_old(DisasContext *s, CPUStat= e *cpu, int b) tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, tr.selector)); ot =3D mod =3D=3D 3 ? dflag : MO_16; - gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, ot, 1); break; case 3: /* ltr */ if (!PE(s) || VM86(s)) goto illegal_op; if (check_cpl0(s)) { gen_svm_check_intercept(s, SVM_EXIT_TR_WRITE); - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, MO_16, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ltr(tcg_env, s->tmp2_i32); } @@ -3625,7 +3616,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) case 5: /* verw */ if (!PE(s) || VM86(s)) goto illegal_op; - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, MO_16, 0); gen_update_cc_op(s); if (op =3D=3D 4) { gen_helper_verr(tcg_env, s->T0); @@ -3889,7 +3880,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) */ mod =3D (modrm >> 6) & 3; ot =3D (mod !=3D 3 ? MO_16 : s->dflag); - gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, ot, 1); break; case 0xee: /* rdpkru */ if (s->prefix & (PREFIX_LOCK | PREFIX_DATA @@ -3916,7 +3907,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) break; } gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, MO_16, 0); /* * Only the 4 lower bits of CR0 are modified. * PE cannot be set to zero if already set to one. @@ -3988,7 +3979,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) ot =3D dflag !=3D MO_16 ? MO_32 : MO_16; modrm =3D x86_ldub_code(env, s); reg =3D ((modrm >> 3) & 7) | REX_R(s); - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, MO_16, 0); t0 =3D tcg_temp_new(); gen_update_cc_op(s); if (b =3D=3D 0x102) { @@ -4492,7 +4483,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 ot =3D dflag; - gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, ot, 0); gen_extu(ot, s->T0); tcg_gen_mov_tl(cpu_cc_src, s->T0); tcg_gen_ctpop_tl(s->T0, s->T0); --=20 2.45.1