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Fri, 24 May 2024 01:10:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHpU5N3NKmoyUY1FhQuVzGs9Gsj+oF21Pz8XGrZixmk4Bt1MkQLZrO5gB+6hivtcUULe0E+Kw== X-Received: by 2002:a17:906:470f:b0:a5c:e240:ceb7 with SMTP id a640c23a62f3a-a6264f0e8c9mr98378866b.62.1716538252765; Fri, 24 May 2024 01:10:52 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 15/16] target/i386: cpu_load_eflags already sets cc_op Date: Fri, 24 May 2024 10:10:18 +0200 Message-ID: <20240524081019.1141359-16-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240524081019.1141359-1-pbonzini@redhat.com> References: <20240524081019.1141359-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716538286789100007 Content-Type: text/plain; charset="utf-8" No need to set it again at the end of the translation block, cc_op_dirty can be set to false. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/translate.c | 37 ++++++++++++++++++++++++------------- target/i386/tcg/emit.c.inc | 2 +- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 1a776e77297..7442a8a51b1 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -332,7 +332,7 @@ static const uint8_t cc_op_live[CC_OP_NB] =3D { [CC_OP_POPCNT] =3D USES_CC_SRC, }; =20 -static void set_cc_op(DisasContext *s, CCOp op) +static void set_cc_op_1(DisasContext *s, CCOp op, bool dirty) { int dead; =20 @@ -355,20 +355,27 @@ static void set_cc_op(DisasContext *s, CCOp op) tcg_gen_discard_tl(s->cc_srcT); } =20 - if (op =3D=3D CC_OP_DYNAMIC) { - /* The DYNAMIC setting is translator only, and should never be - stored. Thus we always consider it clean. */ - s->cc_op_dirty =3D false; - } else { - /* Discard any computed CC_OP value (see shifts). */ - if (s->cc_op =3D=3D CC_OP_DYNAMIC) { - tcg_gen_discard_i32(cpu_cc_op); - } - s->cc_op_dirty =3D true; + if (dirty && s->cc_op =3D=3D CC_OP_DYNAMIC) { + tcg_gen_discard_i32(cpu_cc_op); } + s->cc_op_dirty =3D dirty; s->cc_op =3D op; } =20 +static void set_cc_op(DisasContext *s, CCOp op) +{ + /* + * The DYNAMIC setting is translator only, everything else + * will be spilled later. + */ + set_cc_op_1(s, op, op !=3D CC_OP_DYNAMIC); +} + +static void assume_cc_op(DisasContext *s, CCOp op) +{ + set_cc_op_1(s, op, false); +} + static void gen_update_cc_op(DisasContext *s) { if (s->cc_op_dirty) { @@ -3510,6 +3517,10 @@ static void disas_insn_old(DisasContext *s, CPUState= *cpu, int b) gen_update_cc_op(s); gen_update_eip_cur(s); gen_helper_syscall(tcg_env, cur_insn_len_i32(s)); + /* condition codes are modified only in long mode */ + if (LMA(s)) { + assume_cc_op(s, CC_OP_EFLAGS); + } /* TF handling for the syscall insn is different. The TF bit is c= hecked after the syscall insn completes. This allows #DB to not be generated after one has entered CPL0 if TF is set in FMASK. */ @@ -3526,7 +3537,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) gen_helper_sysret(tcg_env, tcg_constant_i32(dflag - 1)); /* condition codes are modified only in long mode */ if (LMA(s)) { - set_cc_op(s, CC_OP_EFLAGS); + assume_cc_op(s, CC_OP_EFLAGS); } /* TF handling for the sysret insn is different. The TF bit is checked after the sysret insn completes. This allows #DB to= be @@ -4444,7 +4455,7 @@ static void disas_insn_old(DisasContext *s, CPUState = *cpu, int b) g_assert_not_reached(); #else gen_helper_rsm(tcg_env); - set_cc_op(s, CC_OP_EFLAGS); + assume_cc_op(s, CC_OP_EFLAGS); #endif /* CONFIG_USER_ONLY */ s->base.is_jmp =3D DISAS_EOB_ONLY; break; diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 9eecf7ab56c..9fea395dfbf 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1881,7 +1881,7 @@ static void gen_IRET(DisasContext *s, CPUX86State *en= v, X86DecodedInsn *decode) gen_helper_iret_protected(tcg_env, tcg_constant_i32(s->dflag - 1), eip_next_i32(s)); } - set_cc_op(s, CC_OP_EFLAGS); + assume_cc_op(s, CC_OP_EFLAGS); s->base.is_jmp =3D DISAS_EOB_ONLY; } =20 --=20 2.45.1