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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-682227f1838sm87041a12.46.2024.05.23.16.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 16:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716505703; x=1717110503; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nV6w1AjQDLWDB3Npch3KGBEPSiv+4sXlghjNuPVyMEM=; b=bjhin0lYhhaKn78bb+lqf57T8BNYMPIMDBqGbTVcqxlr6doE+oYYKAjIXRezp+JvbN w4HNwaMrboJoDVIZUO4VNJWgQ48SRYALqPCUzKxDDTehBGkG0I7GqIlF/hAynoiXWzjB 1eegN1idd8kjVej4XO2S30QSJGm816lxgChk14kdby4aOyzLoUi0NliEXOXoq2Ale2dx Z9gHVCCcwWxe5OwGg86UvYr4sgARDzd519bMysPyYQanDNAmJ3Otr7iCkm+zlSmNiN9v obJZBql2D44P5F8I6etD7zes8upQnbqP54ZVa2kunfnFBearxzKKRdEAUHuAMJEIkXtI dTug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716505703; x=1717110503; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nV6w1AjQDLWDB3Npch3KGBEPSiv+4sXlghjNuPVyMEM=; b=dxiQPx/FVd62ALAHxhEU7Nv9xtIq2AfPhqV1g1/a12utHWu5QIKzjxfTpxMi1Xyb9q V/kL/Cf26yx/si6r7I/Vb8Vs+rfkxHCROgPenxUfcYBDDmMix+vLFSAvPSGmLFUWjXio aKTSCFELot8r+oyxslcUH9Rh0Zbj6y/MUsdDgKOV27dEoHZWzd0i01J+WeWstUwzTgio dStCGOyjSN8rYz2oNHr+hPRrKYkyKlprD+dfp3pw0030mxEbf4E2ANFLcg8L6DB41Uyw p1Tm/DZGBKi9k5DO8nDzYNSM+UDPPNXdKV7izKzS+VPom+n64Rxj4bRzA/b3mk8mf+LE W2jA== X-Forwarded-Encrypted: i=1; AJvYcCXls2BJ77URuEMDj71/2dhfJkKejsMXFRZ20R5+E1iqvi1PEjkvbSZ4tUmIYswOpX3XMBSMfVi9oLM4M9zij87pbhfe X-Gm-Message-State: AOJu0Yyy91YalgwWY7JNh/qg4PPkYFI/blvGVK14JTNrIJusDpnCzxnX xvwBtrAcTiJFLN1pw5M3wZTB/mwX4jms246zYh4ca1eUSFLZee2jpT32EA== X-Google-Smtp-Source: AGHT+IFo3ln8e9W/4R6ElV65NgjAEj7rFathR3JjZtSEmcbPI5h874VnNAz7cYvZDVREzgpJfcV7TQ== X-Received: by 2002:a17:90b:1093:b0:2bd:8aed:740a with SMTP id 98e67ed59e1d1-2bf5e569480mr615167a91.23.1716505702735; Thu, 23 May 2024 16:08:22 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Chinmay Rath Subject: [PULL 08/72] target/ppc: Add ISA v3.1 variants of sync instruction Date: Fri, 24 May 2024 09:06:41 +1000 Message-ID: <20240523230747.45703-9-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240523230747.45703-1-npiggin@gmail.com> References: <20240523230747.45703-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=npiggin@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1716506022922100009 Content-Type: text/plain; charset="utf-8" POWER10 adds a new field to sync for store-store syncs, and some new variants of the existing syncs that include persistent memory. Implement the store-store syncs and plwsync/phwsync. Reviewed-by: Chinmay Rath Signed-off-by: Nicholas Piggin --- target/ppc/insn32.decode | 6 ++-- target/ppc/translate/misc-impl.c.inc | 41 ++++++++++++++++++++-------- 2 files changed, 32 insertions(+), 15 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 6b89804b15..a180380750 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1001,7 +1001,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - =20 # Memory Barrier Instructions =20 -&X_sync l -@X_sync ...... ... l:2 ..... ..... .......... . &X_sync -SYNC 011111 --- .. ----- ----- 1001010110 - @X_sync +&X_sync l sc +@X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync +SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync EIEIO 011111 ----- ----- ----- 1101010110 - diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index 7574317600..c1661d2f43 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -25,6 +25,7 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a) { TCGBar bar =3D TCG_MO_ALL; uint32_t l =3D a->l; + uint32_t sc =3D a->sc; =20 /* * BookE uses the msync mnemonic. This means hwsync, except in the @@ -41,20 +42,36 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a) return false; } =20 - if ((l =3D=3D 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { - bar =3D TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; - } - /* - * We may need to check for a pending TLB flush. - * - * We do this on ptesync (l =3D=3D 2) on ppc64 and any sync on ppc32. - * - * Additionally, this can only happen in kernel mode however so - * check MSR_PR as well. + * In ISA v3.1, the L field grew one bit. Mask that out to ignore it in + * older processors. It also added the SC field, zero this to ignore + * it too. */ - if (((l =3D=3D 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { - gen_check_tlb_flush(ctx, true); + if (!(ctx->insns_flags2 & PPC2_ISA310)) { + l &=3D 0x3; + sc =3D 0; + } + + if (sc) { + /* Store syncs [stsync, stcisync, stncisync]. These ignore L. */ + bar =3D TCG_MO_ST_ST; + } else { + if (((l =3D=3D 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) || (l = =3D=3D 5)) { + /* lwsync, or plwsync on POWER10 and later */ + bar =3D TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; + } + + /* + * We may need to check for a pending TLB flush. + * + * We do this on ptesync (l =3D=3D 2) on ppc64 and any sync on ppc= 32. + * + * Additionally, this can only happen in kernel mode however so + * check MSR_PR as well. + */ + if (((l =3D=3D 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { + gen_check_tlb_flush(ctx, true); + } } =20 tcg_gen_mb(bar | TCG_BAR_SC); --=20 2.43.0