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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-682227f1838sm87041a12.46.2024.05.23.16.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 16:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716505893; x=1717110693; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qUIv6gOUQGMH2IYnVoR6s2tHYavWJsXfOY+eWwUBs6A=; b=ZjDuldC2Q9HypDeol0QD92Ovlqkknqb38v/QiYh2sput5CVhBMBs08j2NLaJQ98zmi 72/XqKn6p+rQCYSSAyTuc5V5p4hh7gipC7OB762YdevO5IbMaLQfCOij33FbiVn5yE7B IHI4H3OUu/v/2Nzhx4gSts2vJUpx17dqwsSEbiV+7u7qO+J12qpf2flObmtkaaNk22l8 GfvIff1cHzruHNjoNZVe6G7zCKiHDUrNvmyB7jCrsFUr+/0+EIgQXd+0p0UmZQA0kR0C mqf8FxXeAC3KVOqlEDdCrtYZzxzEkhU2TynL5rT6GT4pVTCzXagf6RPBMh/5eC1LtTfV m3KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716505893; x=1717110693; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qUIv6gOUQGMH2IYnVoR6s2tHYavWJsXfOY+eWwUBs6A=; b=Q+LB/6WJCvNTSJXtjnVpB8rObQL0yGQyegUNQxEutNNlNUn+f8rRvuSBt0p39lIko1 0u/1NtEK3vjBl7iHJRVRCCg4OzuJn/HL/OFlgUMe4fhmYxlfeUpZ1dmwK0Z3kABJXDVE CzEBzEo6q2yURw6FSloDDDINCEoc0gBh7FeyJqn5QDbIEFOs8hFtav5prXszEhUGlF0f MC06owTqujG1L8ZQ74g5gt5h1GrLLFw/+zKWkww6Js1JUcP03D/M4I7MQyoAVQKhtFLQ d6yEGJA+e7fn6b0pENdQ0WX5rhcA/YkDZqfuPzk+dbEDcFDs0L+qoVhamYd8uqDEsT8I SRWw== X-Forwarded-Encrypted: i=1; AJvYcCW3DOxDAkSSejgrnIPbYK4o3d6zcyd7rpXoAQcBiIEjJu0ZZO66yroFhowK3BqbmSq+omrlZmx/HcsuuUcGJde4ffrH X-Gm-Message-State: AOJu0YyYyye/6J0s0YiUx7/J5MdGLnmOjL1sjPM8RyBc9QgWOWhOrk+p B+ufYfH5ZWyfmPso9AoOqbYYSmuPwDRcK4oXnRjE+GVk6v/39/yT6fUXDQ== X-Google-Smtp-Source: AGHT+IHqPLTeFCd2/EXj3sO3S/gqnVIsVSbzr5jRBv5DvB4NtUawQ7iISJFJncNgWSXKNkwpI7thAQ== X-Received: by 2002:a05:6358:341d:b0:18d:b8bf:dff with SMTP id e5c5f4694b2df-197e48162a8mr103895155d.0.1716505892421; Thu, 23 May 2024 16:11:32 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan Subject: [PULL 70/72] target/ppc: Add a function to check for page protection bit Date: Fri, 24 May 2024 09:07:43 +1000 Message-ID: <20240523230747.45703-71-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240523230747.45703-1-npiggin@gmail.com> References: <20240523230747.45703-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=npiggin@gmail.com; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1716506459035100001 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan Checking if a page protection bit is set for a given access type is a common operation. Add a function to avoid repeating the same check at multiple places. As this relies on access type and page protection bit values having certain relation also add an assert to ensure that this assumption holds. Reviewed-by: Nicholas Piggin Signed-off-by: BALATON Zoltan Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c | 5 +++++ target/ppc/internal.h | 23 +++++------------------ target/ppc/mmu-hash32.c | 6 +++--- target/ppc/mmu-hash64.c | 2 +- target/ppc/mmu-radix64.c | 2 +- target/ppc/mmu_common.c | 26 +++++++++++++------------- 6 files changed, 28 insertions(+), 36 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index b1ea301e22..01e358a4a5 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7521,6 +7521,11 @@ static void ppc_cpu_class_init(ObjectClass *oc, void= *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &ppc_sysemu_ops; INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics =3D ppc_get_irq_sta= ts; + + /* check_prot_access_type relies on MMU access and PAGE bits relations= */ + qemu_build_assert(MMU_DATA_LOAD =3D=3D 0 && MMU_DATA_STORE =3D=3D 1 && + MMU_INST_FETCH =3D=3D 2 && PAGE_READ =3D=3D 1 && + PAGE_WRITE =3D=3D 2 && PAGE_EXEC =3D=3D 4); #endif =20 cc->gdb_num_core_regs =3D 71; diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 4a90dd2584..20fb2ec593 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -234,27 +234,14 @@ void destroy_ppc_opcodes(PowerPCCPU *cpu); void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *ppc); const gchar *ppc_gdb_arch_name(CPUState *cs); =20 -/** - * prot_for_access_type: - * @access_type: Access type - * - * Return the protection bit required for the given access type. - */ -static inline int prot_for_access_type(MMUAccessType access_type) +#ifndef CONFIG_USER_ONLY + +/* Check if permission bit required for the access_type is set in prot */ +static inline int check_prot_access_type(int prot, MMUAccessType access_ty= pe) { - switch (access_type) { - case MMU_INST_FETCH: - return PAGE_EXEC; - case MMU_DATA_LOAD: - return PAGE_READ; - case MMU_DATA_STORE: - return PAGE_WRITE; - } - g_assert_not_reached(); + return prot & (1 << access_type); } =20 -#ifndef CONFIG_USER_ONLY - /* PowerPC MMU emulation */ =20 bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 3abaf16e78..1e8f1df0f0 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -252,7 +252,7 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, ta= rget_ulong sr, } =20 *prot =3D key ? PAGE_READ | PAGE_WRITE : PAGE_READ; - if (*prot & prot_for_access_type(access_type)) { + if (check_prot_access_type(*prot, access_type)) { *raddr =3D eaddr; return true; } @@ -403,7 +403,7 @@ bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMU= AccessType access_type, if (env->nb_BATs !=3D 0) { raddr =3D ppc_hash32_bat_lookup(cpu, eaddr, access_type, protp, mm= u_idx); if (raddr !=3D -1) { - if (prot_for_access_type(access_type) & ~*protp) { + if (!check_prot_access_type(*protp, access_type)) { if (guest_visible) { if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D POWERPC_EXCP_ISI; @@ -471,7 +471,7 @@ bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMU= AccessType access_type, =20 prot =3D ppc_hash32_pte_prot(mmu_idx, sr, pte); =20 - if (prot_for_access_type(access_type) & ~prot) { + if (!check_prot_access_type(prot, access_type)) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); if (guest_visible) { diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index accbf0b2d8..cbc8efa0c3 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1089,7 +1089,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, amr_prot =3D ppc_hash64_amr_prot(cpu, pte); prot =3D exec_prot & pp_prot & amr_prot; =20 - need_prot =3D prot_for_access_type(access_type); + need_prot =3D check_prot_access_type(PAGE_RWX, access_type); if (need_prot & ~prot) { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index c1e4f00335..5a02e4963b 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -209,7 +209,7 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMU= AccessType access_type, } =20 /* Check if requested access type is allowed */ - if (prot_for_access_type(access_type) & ~*prot) { + if (!check_prot_access_type(*prot, access_type)) { /* Page Protected for that Access */ *fault_cause |=3D access_type =3D=3D MMU_INST_FETCH ? SRR1_NOEXEC_= GUARD : DSISR_PROTFAULT; diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 78bdbd506c..5414a14aad 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -114,11 +114,6 @@ static int pp_check(int key, int pp, int nx) return access; } =20 -static int check_prot(int prot, MMUAccessType access_type) -{ - return prot & prot_for_access_type(access_type) ? 0 : -2; -} - int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, int way, int is_code) { @@ -165,13 +160,14 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, targe= t_ulong pte0, /* Keep the matching PTE information */ ctx->raddr =3D pte1; ctx->prot =3D access; - ret =3D check_prot(ctx->prot, access_type); - if (ret =3D=3D 0) { + if (check_prot_access_type(ctx->prot, access_type)) { /* Access granted */ qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); + ret =3D 0; } else { /* Access right violation */ qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); + ret =3D -2; } } } @@ -354,12 +350,14 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_= t *ctx, (virtual & 0x0001F000); /* Compute access rights */ ctx->prot =3D prot; - ret =3D check_prot(ctx->prot, access_type); - if (ret =3D=3D 0) { + if (check_prot_access_type(ctx->prot, access_type)) { qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " HWADDR_F= MT_plx " prot=3D%c%c\n", i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', ctx->prot & PAGE_WRITE ? 'W' : '-'); + ret =3D 0; + } else { + ret =3D -2; } break; } @@ -576,9 +574,11 @@ static int mmu40x_get_physical_address(CPUPPCState *en= v, hwaddr *raddr, check_perms: /* Check from TLB entry */ *prot =3D tlb->prot; - ret =3D check_prot(*prot, access_type); - if (ret =3D=3D -2) { + if (check_prot_access_type(*prot, access_type)) { + ret =3D 0; + } else { env->spr[SPR_40x_ESR] =3D 0; + ret =3D -2; } break; } @@ -636,7 +636,7 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_= tlb_t *tlb, } else { *prot =3D (tlb->prot >> 4) & 0xF; } - if (*prot & prot_for_access_type(access_type)) { + if (check_prot_access_type(*prot, access_type)) { qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__); return 0; } @@ -838,7 +838,7 @@ found_tlb: *prot |=3D PAGE_EXEC; } } - if (*prot & prot_for_access_type(access_type)) { + if (check_prot_access_type(*prot, access_type)) { qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__); return 0; } --=20 2.43.0