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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-682227f1838sm87041a12.46.2024.05.23.16.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 16:11:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716505870; x=1717110670; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hfWSPhuOjJhkvsLDqYZmW5geyHoP88c+PYL6wv+48vI=; b=cZsjh1nX/iO7fMeEj1IFKbuUM+vHS4gZikRXc3YeXDfWPr4v5SAms49Kwr4soWBt1j iQg3QpA1PlTX6bjB1WRMKU1P0dzyjMEJKXcoOh4690A7xxNwoh+JlzsAqHRdNKdXwkK6 jYvrJsJT6YbZaeLsRcG4xvhsA7MHV0TTC02w0iC3aI3adrBmyDQUgEjkvYVeOivFGwPN 8b2HXOaqN4BNhen1FNyJwwyr+B43oh22LEjlk1DSELNb40y0m+IGohw3iiJUNbZDrRWB C1WsCkOEJhWEB9EgCZd7npkdv/PbgiiUAHv1FK1BhL42h2c1HlhLupCMnC2AWNv1XnFZ HEZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716505870; x=1717110670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hfWSPhuOjJhkvsLDqYZmW5geyHoP88c+PYL6wv+48vI=; b=uakZYtEVVDeOgVW1vQFtPABqFnBzuK0YBJ1Bf8WVDsyNQcg3WonXBGIfbRabQ4Qj2W mo4yMIE7z8nZsvxxm0n94Y+ipPPxmojLh1BzEK15gq1GszihF29ZOmPuxEMZx2P+E3Qt 7FqfONTsSyw869mFJERcpL3ukXnXCNnWlmfcmsDBriRocTUZZevm1StfhhHYiWcpiWg/ Aj+Nbgw4pji+t2dQH24FoNoWT+Fv8KY6YzGnKrs20jDGksYm8A9YlMLlz2TmW4hJMnI+ k5iwSw5Q6thtJr+O4MgqbMMKL6hSrPvphhx3fISBVUEAEKgnin/V4y5G+3cD2UEStYvC ZhtA== X-Forwarded-Encrypted: i=1; AJvYcCVj0hcMBZdDyGrW+WPN3mrcximhve5dCodrQCdMxYEHm2UH3V61UVX4wdkGfUUCMMY+b5N7+M9ZDq+DDZAREWl6krFJ X-Gm-Message-State: AOJu0YwONuqPf1Y4ELki0daGwWiel0Fq2KxMZR2o27ujGXBCy/3Bc4hU m99Dm3xMifCEBISsYGhSzYJxq1GbX7tr/V/+7kJMwmNWNbfkvHP4HsX9fw== X-Google-Smtp-Source: AGHT+IFd4G+Guh2bDb0S0GibyU596gtY0QIN9AjS38DzRcXXAiCv9wM8IU/a8qQnyIgav0i2X3F7wg== X-Received: by 2002:a05:6e02:1a4f:b0:371:bacd:797 with SMTP id e9e14a558f8ab-3737b2df627mr6852575ab.15.1716505870085; Thu, 23 May 2024 16:11:10 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan Subject: [PULL 63/72] target/ppc/mmu_common.c: Split off 40x cases from ppc_jumbo_xlate() Date: Fri, 24 May 2024 09:07:36 +1000 Message-ID: <20240523230747.45703-64-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240523230747.45703-1-npiggin@gmail.com> References: <20240523230747.45703-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12a; envelope-from=npiggin@gmail.com; helo=mail-il1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1716505951064100007 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan Introduce ppc_40x_xlate() to split off 40x handlning leaving only 6xx in ppc_jumbo_xlate() now. Reviewed-by: Nicholas Piggin Signed-off-by: BALATON Zoltan Signed-off-by: Nicholas Piggin --- target/ppc/mmu_common.c | 150 +++++++++++++++++++++++++--------------- 1 file changed, 93 insertions(+), 57 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index ab912da821..ddb014e0aa 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -1258,6 +1258,74 @@ static bool ppc_real_mode_xlate(PowerPCCPU *cpu, vad= dr eaddr, return false; } =20 +static bool ppc_40x_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + int mmu_idx, bool guest_visible) +{ + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; + int ret; + + if (ppc_real_mode_xlate(cpu, eaddr, access_type, raddrp, psizep, protp= )) { + return true; + } + + ret =3D mmu40x_get_physical_address(env, raddrp, protp, eaddr, access_= type); + if (ret =3D=3D 0) { + *psizep =3D TARGET_PAGE_BITS; + return true; + } else if (!guest_visible) { + return false; + } + + log_cpu_state_mask(CPU_LOG_MMU, cs, 0); + if (access_type =3D=3D MMU_INST_FETCH) { + switch (ret) { + case -1: + /* No matches in page tables or TLB */ + cs->exception_index =3D POWERPC_EXCP_ITLB; + env->error_code =3D 0; + env->spr[SPR_40x_DEAR] =3D eaddr; + env->spr[SPR_40x_ESR] =3D 0x00000000; + break; + case -2: + /* Access rights violation */ + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x08000000; + break; + default: + g_assert_not_reached(); + } + } else { + switch (ret) { + case -1: + /* No matches in page tables or TLB */ + cs->exception_index =3D POWERPC_EXCP_DTLB; + env->error_code =3D 0; + env->spr[SPR_40x_DEAR] =3D eaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_40x_ESR] =3D 0x00800000; + } else { + env->spr[SPR_40x_ESR] =3D 0x00000000; + } + break; + case -2: + /* Access rights violation */ + cs->exception_index =3D POWERPC_EXCP_DSI; + env->error_code =3D 0; + env->spr[SPR_40x_DEAR] =3D eaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_40x_ESR] |=3D 0x00800000; + } + break; + default: + g_assert_not_reached(); + } + } + return false; +} + /* Perform address translation */ /* TODO: Split this by mmu_model. */ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, @@ -1301,23 +1369,11 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr = eaddr, switch (ret) { case -1: /* No matches in page tables or TLB */ - switch (env->mmu_model) { - case POWERPC_MMU_SOFT_6xx: - cs->exception_index =3D POWERPC_EXCP_IFTLB; - env->error_code =3D 1 << 18; - env->spr[SPR_IMISS] =3D eaddr; - env->spr[SPR_ICMP] =3D 0x80000000 | ctx.ptem; - goto tlb_miss; - case POWERPC_MMU_SOFT_4xx: - cs->exception_index =3D POWERPC_EXCP_ITLB; - env->error_code =3D 0; - env->spr[SPR_40x_DEAR] =3D eaddr; - env->spr[SPR_40x_ESR] =3D 0x00000000; - break; - default: - g_assert_not_reached(); - } - break; + cs->exception_index =3D POWERPC_EXCP_IFTLB; + env->error_code =3D 1 << 18; + env->spr[SPR_IMISS] =3D eaddr; + env->spr[SPR_ICMP] =3D 0x80000000 | ctx.ptem; + goto tlb_miss; case -2: /* Access rights violation */ cs->exception_index =3D POWERPC_EXCP_ISI; @@ -1339,54 +1395,31 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr = eaddr, switch (ret) { case -1: /* No matches in page tables or TLB */ - switch (env->mmu_model) { - case POWERPC_MMU_SOFT_6xx: - if (access_type =3D=3D MMU_DATA_STORE) { - cs->exception_index =3D POWERPC_EXCP_DSTLB; - env->error_code =3D 1 << 16; - } else { - cs->exception_index =3D POWERPC_EXCP_DLTLB; - env->error_code =3D 0; - } - env->spr[SPR_DMISS] =3D eaddr; - env->spr[SPR_DCMP] =3D 0x80000000 | ctx.ptem; - tlb_miss: - env->error_code |=3D ctx.key << 19; - env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(cpu) + - get_pteg_offset32(cpu, ctx.hash[0]); - env->spr[SPR_HASH2] =3D ppc_hash32_hpt_base(cpu) + - get_pteg_offset32(cpu, ctx.hash[1]); - break; - case POWERPC_MMU_SOFT_4xx: - cs->exception_index =3D POWERPC_EXCP_DTLB; + if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D POWERPC_EXCP_DSTLB; + env->error_code =3D 1 << 16; + } else { + cs->exception_index =3D POWERPC_EXCP_DLTLB; env->error_code =3D 0; - env->spr[SPR_40x_DEAR] =3D eaddr; - if (access_type =3D=3D MMU_DATA_STORE) { - env->spr[SPR_40x_ESR] =3D 0x00800000; - } else { - env->spr[SPR_40x_ESR] =3D 0x00000000; - } - break; - default: - g_assert_not_reached(); } + env->spr[SPR_DMISS] =3D eaddr; + env->spr[SPR_DCMP] =3D 0x80000000 | ctx.ptem; +tlb_miss: + env->error_code |=3D ctx.key << 19; + env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(cpu) + + get_pteg_offset32(cpu, ctx.hash[0]); + env->spr[SPR_HASH2] =3D ppc_hash32_hpt_base(cpu) + + get_pteg_offset32(cpu, ctx.hash[1]); break; case -2: /* Access rights violation */ cs->exception_index =3D POWERPC_EXCP_DSI; env->error_code =3D 0; - if (env->mmu_model =3D=3D POWERPC_MMU_SOFT_4xx) { - env->spr[SPR_40x_DEAR] =3D eaddr; - if (access_type =3D=3D MMU_DATA_STORE) { - env->spr[SPR_40x_ESR] |=3D 0x00800000; - } + env->spr[SPR_DAR] =3D eaddr; + if (access_type =3D=3D MMU_DATA_STORE) { + env->spr[SPR_DSISR] =3D 0x0A000000; } else { - env->spr[SPR_DAR] =3D eaddr; - if (access_type =3D=3D MMU_DATA_STORE) { - env->spr[SPR_DSISR] =3D 0x0A000000; - } else { - env->spr[SPR_DSISR] =3D 0x08000000; - } + env->spr[SPR_DSISR] =3D 0x08000000; } break; case -4: @@ -1462,6 +1495,9 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAcces= sType access_type, case POWERPC_MMU_BOOKE206: return ppc_booke_xlate(cpu, eaddr, access_type, raddrp, psizep, protp, mmu_idx, guest_visible); + case POWERPC_MMU_SOFT_4xx: + return ppc_40x_xlate(cpu, eaddr, access_type, raddrp, + psizep, protp, mmu_idx, guest_visible); case POWERPC_MMU_REAL: return ppc_real_mode_xlate(cpu, eaddr, access_type, raddrp, psizep, protp); --=20 2.43.0