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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-682227f1838sm87041a12.46.2024.05.23.16.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 16:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716505858; x=1717110658; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j0OIGWXGUbgVeZfHYAO7jVYpw/01X/ceVaPnQiECOqQ=; b=MSUCjLR5TC5lCMypSic6FB0omyMGORJo/lbNphnXjzub1i8dQ8rH2qFME6jtDxz7iu a4tUhPE/wuJA+Op4XnFWqVlXQzsLYisShHWurvOP5Dw1fWTYYMCniox/KZBSAgM0Kw+O ZNWUd20BJ1aSovce+v0b+dFHA/YQZE7f1OPrMmrAr2gQWS0OzZoaur9rPEhCcLZ+2xjq 1sYf/4DlfoQh2Kaz25UOxHHMbVZSd7Jxblx8jLN47/LtEao323qKDyj1KUXswe6gtNnX V9oqivFkYW6oKm/ca0aOIh25dpo2lazvsGmZicamV2G78Lb9Nllu9J1xaQlmPfuWy4N6 d7cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716505858; x=1717110658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j0OIGWXGUbgVeZfHYAO7jVYpw/01X/ceVaPnQiECOqQ=; b=vu3447G0E3vz66kjeWABp+m6n5wIbeOIh/BASbW2eRfbZCz+tpLeY3AZEk8tk1Mhmp KmH1VxyfRWNqzlT3wZre0+whrJ9GtI8iuADaQvI4jQwrZS3muzuOw/58TnFazNxf9Nxa FMzmcxKUMTumZBvdINexYZJSFxCX5upmZviu5e2EFRQsWj4o7dSVo0b6y1k37N6cv94Q RCrwwZa3E0vimhW5vlYxskvHoZqj7+c9yxn3WYeCLahdssRUJGLFV+kOzjVA44ki8jt5 3u4zoodN66heUUXYw1s22LiKinWmM6D7qg1hTdRDpj+052Mxe+DDwNlLihdZxh3uV8lb zNcg== X-Forwarded-Encrypted: i=1; AJvYcCXuh4jp63c2kJby9PCc0/1WPITHRD+RB+XH5BML/P7k9+PMdGNxnKwJv2wJR/Y9xBxQNEuGtvsJp2HvKVA/jVPMTyAD X-Gm-Message-State: AOJu0YwoT2wc6X4bfp/yFopvzvv/RvD5fAiHJ/W9nOR0ahLzWNPzqdOH ue2jHOhTyPD5fQjTWYBiQLuLyY31KZ5MCB1+YVsgv/VWgRxdUx797T4Q0g== X-Google-Smtp-Source: AGHT+IG/7cN/LaMJM6BEXAd8Q+9ADj9aDoBOKRU5TyyKEpeIFDyLfbwjIoBCdi0cPrkO4RTjur7Jwg== X-Received: by 2002:a05:6a00:4c12:b0:6f3:ea67:48c3 with SMTP id d2e1a72fcca58-6f8f1a66df5mr802438b3a.0.1716505857713; Thu, 23 May 2024 16:10:57 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan Subject: [PULL 59/72] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() Date: Fri, 24 May 2024 09:07:32 +1000 Message-ID: <20240523230747.45703-60-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240523230747.45703-1-npiggin@gmail.com> References: <20240523230747.45703-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1716506209847100001 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to reduce ppc_jumbo_xlate() further. Reviewed-by: Nicholas Piggin Signed-off-by: BALATON Zoltan Signed-off-by: Nicholas Piggin --- target/ppc/mmu_common.c | 146 ++++++++++++++++++++++++++-------------- 1 file changed, 96 insertions(+), 50 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 6c6c7c55b6..09a780bb7a 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -1117,21 +1117,9 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_= ctx_t *ctx, MMUAccessType access_type, int type, int mmu_idx) { - bool real_mode; - - if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE) { - return mmubooke_get_physical_address(env, &ctx->raddr, &ctx->prot, - eaddr, access_type); - } else if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) { - return mmubooke206_get_physical_address(env, &ctx->raddr, &ctx->pr= ot, - eaddr, access_type, mmu_id= x); - } - - real_mode =3D (type =3D=3D ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR, I= R) - : !FIELD_EX64(env->msr, MSR, DR); - if (real_mode && (env->mmu_model =3D=3D POWERPC_MMU_SOFT_6xx || - env->mmu_model =3D=3D POWERPC_MMU_SOFT_4xx || - env->mmu_model =3D=3D POWERPC_MMU_REAL)) { + bool real_mode =3D (type =3D=3D ACCESS_CODE) ? !FIELD_EX64(env->msr, M= SR, IR) + : !FIELD_EX64(env->msr, MSR, DR= ); + if (real_mode) { ctx->raddr =3D eaddr; ctx->prot =3D PAGE_RWX; return 0; @@ -1205,6 +1193,93 @@ static void booke206_update_mas_tlb_miss(CPUPPCState= *env, target_ulong address, env->spr[SPR_BOOKE_MAS0] |=3D env->last_way << MAS0_NV_SHIFT; } =20 +static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, + hwaddr *raddrp, int *psizep, int *protp, + int mmu_idx, bool guest_visible) +{ + CPUState *cs =3D CPU(cpu); + CPUPPCState *env =3D &cpu->env; + hwaddr raddr; + int prot, ret; + + if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) { + ret =3D mmubooke206_get_physical_address(env, &raddr, &prot, eaddr, + access_type, mmu_idx); + } else { + ret =3D mmubooke_get_physical_address(env, &raddr, &prot, eaddr, + access_type); + } + if (ret =3D=3D 0) { + *raddrp =3D raddr; + *protp =3D prot; + *psizep =3D TARGET_PAGE_BITS; + return true; + } else if (!guest_visible) { + return false; + } + + log_cpu_state_mask(CPU_LOG_MMU, cs, 0); + if (access_type =3D=3D MMU_INST_FETCH) { + switch (ret) { + case -1: + /* No matches in page tables or TLB */ + switch (env->mmu_model) { + case POWERPC_MMU_BOOKE206: + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_= idx); + /* fall through */ + case POWERPC_MMU_BOOKE: + cs->exception_index =3D POWERPC_EXCP_ITLB; + env->error_code =3D 0; + env->spr[SPR_BOOKE_DEAR] =3D eaddr; + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acces= s_type); + break; + default: + g_assert_not_reached(); + } + break; + case -2: + /* Access rights violation */ + cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0; + break; + case -3: + /* No execute protection violation */ + cs->exception_index =3D POWERPC_EXCP_ISI; + env->spr[SPR_BOOKE_ESR] =3D 0; + env->error_code =3D 0; + break; + } + } else { + switch (ret) { + case -1: + /* No matches in page tables or TLB */ + switch (env->mmu_model) { + case POWERPC_MMU_BOOKE206: + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_= idx); + /* fall through */ + case POWERPC_MMU_BOOKE: + cs->exception_index =3D POWERPC_EXCP_DTLB; + env->error_code =3D 0; + env->spr[SPR_BOOKE_DEAR] =3D eaddr; + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acces= s_type); + break; + default: + g_assert_not_reached(); + } + break; + case -2: + /* Access rights violation */ + cs->exception_index =3D POWERPC_EXCP_DSI; + env->error_code =3D 0; + env->spr[SPR_BOOKE_DEAR] =3D eaddr; + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, access_ty= pe); + break; + } + } + return false; +} + /* Perform address translation */ /* TODO: Split this by mmu_model. */ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, @@ -1257,15 +1332,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr e= addr, env->spr[SPR_40x_DEAR] =3D eaddr; env->spr[SPR_40x_ESR] =3D 0x00000000; break; - case POWERPC_MMU_BOOKE206: - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_= idx); - /* fall through */ - case POWERPC_MMU_BOOKE: - cs->exception_index =3D POWERPC_EXCP_ITLB; - env->error_code =3D 0; - env->spr[SPR_BOOKE_DEAR] =3D eaddr; - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acces= s_type); - break; case POWERPC_MMU_REAL: cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); @@ -1276,23 +1342,12 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr = eaddr, case -2: /* Access rights violation */ cs->exception_index =3D POWERPC_EXCP_ISI; - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { - env->error_code =3D 0; - } else { - env->error_code =3D 0x08000000; - } + env->error_code =3D 0x08000000; break; case -3: /* No execute protection violation */ - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { - env->spr[SPR_BOOKE_ESR] =3D 0x00000000; - env->error_code =3D 0; - } else { - env->error_code =3D 0x10000000; - } cs->exception_index =3D POWERPC_EXCP_ISI; + env->error_code =3D 0x10000000; break; case -4: /* Direct store exception */ @@ -1333,15 +1388,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr e= addr, env->spr[SPR_40x_ESR] =3D 0x00000000; } break; - case POWERPC_MMU_BOOKE206: - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_= idx); - /* fall through */ - case POWERPC_MMU_BOOKE: - cs->exception_index =3D POWERPC_EXCP_DTLB; - env->error_code =3D 0; - env->spr[SPR_BOOKE_DEAR] =3D eaddr; - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acces= s_type); - break; case POWERPC_MMU_REAL: cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); @@ -1358,10 +1404,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr e= addr, if (access_type =3D=3D MMU_DATA_STORE) { env->spr[SPR_40x_ESR] |=3D 0x00800000; } - } else if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { - env->spr[SPR_BOOKE_DEAR] =3D eaddr; - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acces= s_type); } else { env->spr[SPR_DAR] =3D eaddr; if (access_type =3D=3D MMU_DATA_STORE) { @@ -1440,6 +1482,10 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAcce= ssType access_type, case POWERPC_MMU_32B: return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp, psizep, protp, mmu_idx, guest_visible); + case POWERPC_MMU_BOOKE: + case POWERPC_MMU_BOOKE206: + return ppc_booke_xlate(cpu, eaddr, access_type, raddrp, + psizep, protp, mmu_idx, guest_visible); case POWERPC_MMU_MPC8xx: cpu_abort(env_cpu(&cpu->env), "MPC8xx MMU model is not implemented= \n"); default: --=20 2.43.0