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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-682227f1838sm87041a12.46.2024.05.23.16.08.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 16:08:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716505694; x=1717110494; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rTU3YRtFQJnscRLORpazwzFhMRi8nDXQ8CTx8TmsNlc=; b=NJchB7+h52jMrRLLZ0J0dX0GdgFtGXxEpO3BxidVDzCdh97zWTxZe0pyU3Yov4Jd6y A7+TR5z4IZTrkOrfmrQ0wMY0eSNEg35qCslM3AhbyEKxG8HBPtsCVFR3Gy+vqrG6Hzav Fjc7Cvg90mRGdT+laQ9/2xBo5ZIFJYyBCCBNWrFNZgqRzF37YQCPVa8AvJ4chS2g3sWl Z0r0NkPxNdzwQY1JXT2qIZJC7aGiT6OQhCul9VRQ9CucRujfzHceDUoTVOdXXd/abKeK OOm/T43UGpzq4pd9sxl/Ch9OhBEQES4hGgbWAO/cUVWhgJoMAQ5V2dMN0MkMpgK17881 Q4JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716505694; x=1717110494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rTU3YRtFQJnscRLORpazwzFhMRi8nDXQ8CTx8TmsNlc=; b=gz4bahGKkeUdzG9DcEXBx3i0ClRnF7t5ZUjp9t6nkjyV7kqcRjKokgmD9scrsJPw81 Mef4uVvexKbluYxrfDNdw91N81KRceX/r+pEmXGTATGCetSohxu1fopf9qNxAcaPw6Jm aQpaWfIkXzn7nCV0Cjwyhz+KBOy2TuxNMBKzapqvN+juNHXdkdmTlH3uUqDVPeygcvnE IGHVvJ2Db/YBKoox5/U8TZ/mWThwmr/wVKMzXTHNFgKa7I2oSF8pyGQBmjuGNKM3FL6I 5h8hpN+Xn2z2ePHvTvWET3x6uGR+BiiC4Si1I4XTrIXdiVF0K3mwSJIl6TlSGbhdvCCv wKkQ== X-Forwarded-Encrypted: i=1; AJvYcCV3ptJcnrYz1Ad1ciVHXxELLOnEGTClQd79WDTsfqDKMsY0f4eQ8O57r7WEKIYs7UnylvQkqAZi/Xr/KXbX3/eqIphw X-Gm-Message-State: AOJu0YzgUUKFRRlle09r4n497nmthBEfvIgujSlzDNKY+hXvKkHwnS97 C2jZ6LCe2CE+IAr98raxZatfKUtGmYvldR7IHjVILhRKeur62Wy/k9aNyQ== X-Google-Smtp-Source: AGHT+IHezfNCx1LOEUiX1pZzgMb7iVoIvqNedfoP+VW1cjtWhC1geLVycnvGcbcSYqf0JSvMVu9dGQ== X-Received: by 2002:a17:90a:c08d:b0:2bd:faa4:e075 with SMTP id 98e67ed59e1d1-2bdfaa4e0a1mr2538006a91.6.1716505693595; Thu, 23 May 2024 16:08:13 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Richard Henderson Subject: [PULL 05/72] tcg/cputlb: remove other-cpu capability from TLB flushing Date: Fri, 24 May 2024 09:06:38 +1000 Message-ID: <20240523230747.45703-6-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240523230747.45703-1-npiggin@gmail.com> References: <20240523230747.45703-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=npiggin@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1716506095227100002 Content-Type: text/plain; charset="utf-8" Some TLB flush operations can flush other CPUs. The problem with this is they used non-synced variants of flushes (i.e., that return before the destination has completed the flush). Since all TLB flush users need the _synced variants, and that last user (ppc) of the non-synced flush was buggy, this is a footgun waiting to go off. There do not seem to be any callers that flush other CPUs, so remove the capability. Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- accel/tcg/cputlb.c | 42 +++++++++--------------------------------- 1 file changed, 9 insertions(+), 33 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 45799869eb..117b516739 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -418,12 +418,9 @@ void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxma= p) { tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); =20 - if (cpu->created && !qemu_cpu_is_self(cpu)) { - async_run_on_cpu(cpu, tlb_flush_by_mmuidx_async_work, - RUN_ON_CPU_HOST_INT(idxmap)); - } else { - tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(idxmap)); - } + assert_cpu_is_self(cpu); + + tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(idxmap)); } =20 void tlb_flush(CPUState *cpu) @@ -612,28 +609,12 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr ad= dr, uint16_t idxmap) { tlb_debug("addr: %016" VADDR_PRIx " mmu_idx:%" PRIx16 "\n", addr, idxm= ap); =20 + assert_cpu_is_self(cpu); + /* This should already be page aligned */ addr &=3D TARGET_PAGE_MASK; =20 - if (qemu_cpu_is_self(cpu)) { - tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap); - } else if (idxmap < TARGET_PAGE_SIZE) { - /* - * Most targets have only a few mmu_idx. In the case where - * we can stuff idxmap into the low TARGET_PAGE_BITS, avoid - * allocating memory for this operation. - */ - async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_1, - RUN_ON_CPU_TARGET_PTR(addr | idxmap)); - } else { - TLBFlushPageByMMUIdxData *d =3D g_new(TLBFlushPageByMMUIdxData, 1); - - /* Otherwise allocate a structure, freed by the worker. */ - d->addr =3D addr; - d->idxmap =3D idxmap; - async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_2, - RUN_ON_CPU_HOST_PTR(d)); - } + tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap); } =20 void tlb_flush_page(CPUState *cpu, vaddr addr) @@ -796,6 +777,8 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr add= r, { TLBFlushRangeData d; =20 + assert_cpu_is_self(cpu); + /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. @@ -816,14 +799,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr ad= dr, d.idxmap =3D idxmap; d.bits =3D bits; =20 - if (qemu_cpu_is_self(cpu)) { - tlb_flush_range_by_mmuidx_async_0(cpu, d); - } else { - /* Otherwise allocate a structure, freed by the worker. */ - TLBFlushRangeData *p =3D g_memdup(&d, sizeof(d)); - async_run_on_cpu(cpu, tlb_flush_range_by_mmuidx_async_1, - RUN_ON_CPU_HOST_PTR(p)); - } + tlb_flush_range_by_mmuidx_async_0(cpu, d); } =20 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, --=20 2.43.0