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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-682227f1838sm87041a12.46.2024.05.23.16.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 16:10:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716505825; x=1717110625; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lbuMqArijPah/JHN3K7DT5Fm7sQv+gbrEinFPcFcrTg=; b=f3dMw4QUmL4oot11Uz6L5iz6n6zUtRf0hDMpaknjt4lUh7FjtJ2dtIdBFjCPoqG84B /UJX/Dqx6JlY4KiIcSH8DGY7iH/JG9+F9B4rRTj8AOVc4RgngbsrcYG5it61BSqPX313 eBoI0n/JJLG/Jp8Phg7w5PRll/fp0gt/RGHh2VUGk/mlD76MysRyYE8PmPRe8Xl+ch7m 189YPPwEVSX6IjGyy/lmbq4OTDnwyJqk0CtC01nKSKOrl22gDjrSNVmJxNHo6KhgFo5c QN2/ckT2rvv6ZxQEt21s7DUfkPah0Zxct51Dv1AejOQnekB/xyVqHOMYfsjlh7juVEIW tcNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716505825; x=1717110625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lbuMqArijPah/JHN3K7DT5Fm7sQv+gbrEinFPcFcrTg=; b=MZq1WgG5goDwVP341oistfNbWxWPyteos0XPcWVLDczdL1pWKUzgo1Ab/b2bZeIfaO 7YPoQfqOXrgExUX8/YlC6YPQ3COtlaJ7Cp2crewRoNRGuhwqYr/omDBhR8Ydizk4U2+J pakJ+xnStG9BLqfnac7W6z0IaGJ2OZKKp1vbhdopixB24HDyr8WXIdVHFlxMVyuobPk2 6heTQWw1tEG/gNtCC0lx/H5FlPz5kZNG6cvxVAvRLlRm9P0P6n8mG66YGS/uaJ++9dYH BkeHeQgH4nFQD8YXb3w/0x2ceAE5G8tkdxj3Sw6ZbVwjacWNnA84zDLfHRCjeprD/y93 MD+g== X-Forwarded-Encrypted: i=1; AJvYcCU/CbQa9LzJkJcBILqWkQVrOtDTTw0uEB/cFV4iPeOCFQdWHKwEmY1oavH0qrPVEI8kchFEgEI/+KswLDOlz+dG/PGI X-Gm-Message-State: AOJu0YzFW0HbVq04kg7UUWTz+xoQmv4SZ4+ZPlrfm5wtY29rwAbvVvUW /jJ34Qdf9RfZGY4/ixPo8TFuUnknLXhvHuWXczjU5eC2pFySyGaZCj9n7w== X-Google-Smtp-Source: AGHT+IGXPrzpQwu9nsObc2dhfPnwNv9pH0aPi6dFQHGwpXlIXB5GMBwQVAAMnmtWh4CpKboZvWFxBw== X-Received: by 2002:a05:6a20:7f93:b0:1b1:ed9d:f92e with SMTP id adf61e73a8af0-1b212e144d2mr1133483637.38.1716505824920; Thu, 23 May 2024 16:10:24 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan Subject: [PULL 48/72] target/ppc/mmu_common.c: Eliminate ret from mmu6xx_get_physical_address() Date: Fri, 24 May 2024 09:07:21 +1000 Message-ID: <20240523230747.45703-49-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240523230747.45703-1-npiggin@gmail.com> References: <20240523230747.45703-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1716505988742100002 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan Return directly, which is simpler than dragging a return value through multpile if and else blocks. Reviewed-by: Nicholas Piggin Signed-off-by: BALATON Zoltan Signed-off-by: Nicholas Piggin --- target/ppc/mmu_common.c | 84 +++++++++++++++++++---------------------- 1 file changed, 39 insertions(+), 45 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 89bfd9aa45..03d9e6bfda 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -386,7 +386,6 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, target_ulong vsid, sr, pgidx; int ds, target_page_bits; bool pr; - int ret; =20 /* First try to find a BAT entry if there are any */ if (env->nb_BATs && get_bat_6xx_tlb(env, ctx, eaddr, access_type) =3D= =3D 0) { @@ -419,7 +418,6 @@ static int mmu6xx_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, qemu_log_mask(CPU_LOG_MMU, "pte segment: key=3D%d ds %d nx %d vsid " TARGET_FMT_lx "\n", ctx->key, ds, ctx->nx, vsid); - ret =3D -1; if (!ds) { /* Check if instruction fetch is allowed, if needed */ if (type =3D=3D ACCESS_CODE && ctx->nx) { @@ -436,51 +434,47 @@ static int mmu6xx_get_physical_address(CPUPPCState *e= nv, mmu_ctx_t *ctx, /* Initialize real address with an invalid value */ ctx->raddr =3D (hwaddr)-1ULL; /* Software TLB search */ - ret =3D ppc6xx_tlb_check(env, ctx, eaddr, access_type); - } else { - qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); - /* Direct-store segment : absolutely *BUGGY* for now */ - - switch (type) { - case ACCESS_INT: - /* Integer load/store : only access allowed */ - break; - case ACCESS_CODE: - /* No code fetch is allowed in direct-store areas */ - return -4; - case ACCESS_FLOAT: - /* Floating point load/store */ - return -4; - case ACCESS_RES: - /* lwarx, ldarx or srwcx. */ - return -4; - case ACCESS_CACHE: - /* - * dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi - * - * Should make the instruction do no-op. As it already do - * no-op, it's quite easy :-) - */ - ctx->raddr =3D eaddr; - return 0; - case ACCESS_EXT: - /* eciwx or ecowx */ - return -4; - default: - qemu_log_mask(CPU_LOG_MMU, "ERROR: instruction should not need= " - "address translation\n"); - return -4; - } - if ((access_type =3D=3D MMU_DATA_STORE || ctx->key !=3D 1) && - (access_type =3D=3D MMU_DATA_LOAD || ctx->key !=3D 0)) { - ctx->raddr =3D eaddr; - ret =3D 2; - } else { - ret =3D -2; - } + return ppc6xx_tlb_check(env, ctx, eaddr, access_type); } =20 - return ret; + /* Direct-store segment : absolutely *BUGGY* for now */ + qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); + switch (type) { + case ACCESS_INT: + /* Integer load/store : only access allowed */ + break; + case ACCESS_CODE: + /* No code fetch is allowed in direct-store areas */ + return -4; + case ACCESS_FLOAT: + /* Floating point load/store */ + return -4; + case ACCESS_RES: + /* lwarx, ldarx or srwcx. */ + return -4; + case ACCESS_CACHE: + /* + * dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi + * + * Should make the instruction do no-op. As it already do + * no-op, it's quite easy :-) + */ + ctx->raddr =3D eaddr; + return 0; + case ACCESS_EXT: + /* eciwx or ecowx */ + return -4; + default: + qemu_log_mask(CPU_LOG_MMU, "ERROR: instruction should not need add= ress" + " translation\n"); + return -4; + } + if ((access_type =3D=3D MMU_DATA_STORE || ctx->key !=3D 1) && + (access_type =3D=3D MMU_DATA_LOAD || ctx->key !=3D 0)) { + ctx->raddr =3D eaddr; + return 2; + } + return -2; } =20 /* Generic TLB check function for embedded PowerPC implementations */ --=20 2.43.0