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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716478855853100005 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20240506010403.6204-14-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/helper-a64.h | 4 + target/arm/tcg/translate.h | 5 + target/arm/tcg/a64.decode | 27 +++++ target/arm/tcg/translate-a64.c | 205 +++++++++++++++++---------------- target/arm/tcg/vec_helper.c | 4 + 5 files changed, 143 insertions(+), 102 deletions(-) diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index b79751a7170..371388f61b5 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -133,6 +133,10 @@ DEF_HELPER_4(cpyfp, void, env, i32, i32, i32) DEF_HELPER_4(cpyfm, void, env, i32, i32, i32) DEF_HELPER_4(cpyfe, void, env, i32, i32, i32) =20 +DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) + DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 80e85096a83..ecfa242eef3 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -252,6 +252,11 @@ static inline int shl_12(DisasContext *s, int x) return x << 12; } =20 +static inline int xor_2(DisasContext *s, int x) +{ + return x ^ 2; +} + static inline int neon_3same_fp_size(DisasContext *s, int x) { /* Convert 0=3D=3Dfp32, 1=3D=3Dfp16 into a MO_* value */ diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 2e0e01be017..82daafbef52 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -21,6 +21,7 @@ =20 %rd 0:5 %esz_sd 22:1 !function=3Dplus_2 +%esz_hsd 22:2 !function=3Dxor_2 %hl 11:1 21:1 %hlm 11:1 20:2 =20 @@ -37,6 +38,7 @@ =20 @rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3D1 @rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3D%esz_= sd +@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3D%esz_= hsd =20 @rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=3D1 idx= =3D%hlm @rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=3D2 idx= =3D%hl @@ -697,22 +699,47 @@ INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5= rd:5 =20 ### Advanced SIMD scalar three same =20 +FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd +FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd +FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd +FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd + FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd =20 ### Advanced SIMD three same =20 +FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h +FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd + +FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h +FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd + +FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h +FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd + +FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h +FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd + FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd =20 ### Advanced SIMD scalar x indexed element =20 +FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h +FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s +FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d + FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d =20 ### Advanced SIMD vector x indexed element =20 +FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h +FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s +FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d + FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 04da374e86d..46976b55826 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4887,6 +4887,34 @@ static bool do_fp3_scalar(DisasContext *s, arg_rrr_e= *a, const FPScalar *f) return true; } =20 +static const FPScalar f_scalar_fadd =3D { + gen_helper_vfp_addh, + gen_helper_vfp_adds, + gen_helper_vfp_addd, +}; +TRANS(FADD_s, do_fp3_scalar, a, &f_scalar_fadd) + +static const FPScalar f_scalar_fsub =3D { + gen_helper_vfp_subh, + gen_helper_vfp_subs, + gen_helper_vfp_subd, +}; +TRANS(FSUB_s, do_fp3_scalar, a, &f_scalar_fsub) + +static const FPScalar f_scalar_fdiv =3D { + gen_helper_vfp_divh, + gen_helper_vfp_divs, + gen_helper_vfp_divd, +}; +TRANS(FDIV_s, do_fp3_scalar, a, &f_scalar_fdiv) + +static const FPScalar f_scalar_fmul =3D { + gen_helper_vfp_mulh, + gen_helper_vfp_muls, + gen_helper_vfp_muld, +}; +TRANS(FMUL_s, do_fp3_scalar, a, &f_scalar_fmul) + static const FPScalar f_scalar_fmulx =3D { gen_helper_advsimd_mulxh, gen_helper_vfp_mulxs, @@ -4922,6 +4950,34 @@ static bool do_fp3_vector(DisasContext *s, arg_qrrr_= e *a, return true; } =20 +static gen_helper_gvec_3_ptr * const f_vector_fadd[3] =3D { + gen_helper_gvec_fadd_h, + gen_helper_gvec_fadd_s, + gen_helper_gvec_fadd_d, +}; +TRANS(FADD_v, do_fp3_vector, a, f_vector_fadd) + +static gen_helper_gvec_3_ptr * const f_vector_fsub[3] =3D { + gen_helper_gvec_fsub_h, + gen_helper_gvec_fsub_s, + gen_helper_gvec_fsub_d, +}; +TRANS(FSUB_v, do_fp3_vector, a, f_vector_fsub) + +static gen_helper_gvec_3_ptr * const f_vector_fdiv[3] =3D { + gen_helper_gvec_fdiv_h, + gen_helper_gvec_fdiv_s, + gen_helper_gvec_fdiv_d, +}; +TRANS(FDIV_v, do_fp3_vector, a, f_vector_fdiv) + +static gen_helper_gvec_3_ptr * const f_vector_fmul[3] =3D { + gen_helper_gvec_fmul_h, + gen_helper_gvec_fmul_s, + gen_helper_gvec_fmul_d, +}; +TRANS(FMUL_v, do_fp3_vector, a, f_vector_fmul) + static gen_helper_gvec_3_ptr * const f_vector_fmulx[3] =3D { gen_helper_gvec_fmulx_h, gen_helper_gvec_fmulx_s, @@ -4975,6 +5031,7 @@ static bool do_fp3_scalar_idx(DisasContext *s, arg_rr= x_e *a, const FPScalar *f) return true; } =20 +TRANS(FMUL_si, do_fp3_scalar_idx, a, &f_scalar_fmul) TRANS(FMULX_si, do_fp3_scalar_idx, a, &f_scalar_fmulx) =20 static bool do_fp3_vector_idx(DisasContext *s, arg_qrrx_e *a, @@ -5005,6 +5062,13 @@ static bool do_fp3_vector_idx(DisasContext *s, arg_q= rrx_e *a, return true; } =20 +static gen_helper_gvec_3_ptr * const f_vector_idx_fmul[3] =3D { + gen_helper_gvec_fmul_idx_h, + gen_helper_gvec_fmul_idx_s, + gen_helper_gvec_fmul_idx_d, +}; +TRANS(FMUL_vi, do_fp3_vector_idx, a, f_vector_idx_fmul) + static gen_helper_gvec_3_ptr * const f_vector_idx_fmulx[3] =3D { gen_helper_gvec_fmulx_idx_h, gen_helper_gvec_fmulx_idx_s, @@ -6827,18 +6891,6 @@ static void handle_fp_2src_single(DisasContext *s, i= nt opcode, tcg_op2 =3D read_fp_sreg(s, rm); =20 switch (opcode) { - case 0x0: /* FMUL */ - gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x1: /* FDIV */ - gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x2: /* FADD */ - gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x3: /* FSUB */ - gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x4: /* FMAX */ gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -6855,6 +6907,12 @@ static void handle_fp_2src_single(DisasContext *s, i= nt opcode, gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); gen_helper_vfp_negs(tcg_res, tcg_res); break; + default: + case 0x0: /* FMUL */ + case 0x1: /* FDIV */ + case 0x2: /* FADD */ + case 0x3: /* FSUB */ + g_assert_not_reached(); } =20 write_fp_sreg(s, rd, tcg_res); @@ -6875,18 +6933,6 @@ static void handle_fp_2src_double(DisasContext *s, i= nt opcode, tcg_op2 =3D read_fp_dreg(s, rm); =20 switch (opcode) { - case 0x0: /* FMUL */ - gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x1: /* FDIV */ - gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x2: /* FADD */ - gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x3: /* FSUB */ - gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x4: /* FMAX */ gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -6903,6 +6949,12 @@ static void handle_fp_2src_double(DisasContext *s, i= nt opcode, gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); gen_helper_vfp_negd(tcg_res, tcg_res); break; + default: + case 0x0: /* FMUL */ + case 0x1: /* FDIV */ + case 0x2: /* FADD */ + case 0x3: /* FSUB */ + g_assert_not_reached(); } =20 write_fp_dreg(s, rd, tcg_res); @@ -6923,18 +6975,6 @@ static void handle_fp_2src_half(DisasContext *s, int= opcode, tcg_op2 =3D read_fp_hreg(s, rm); =20 switch (opcode) { - case 0x0: /* FMUL */ - gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x1: /* FDIV */ - gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x2: /* FADD */ - gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x3: /* FSUB */ - gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x4: /* FMAX */ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -6952,6 +6992,10 @@ static void handle_fp_2src_half(DisasContext *s, int= opcode, tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); break; default: + case 0x0: /* FMUL */ + case 0x1: /* FDIV */ + case 0x2: /* FADD */ + case 0x3: /* FSUB */ g_assert_not_reached(); } =20 @@ -9173,9 +9217,6 @@ static void handle_3same_float(DisasContext *s, int s= ize, int elements, case 0x18: /* FMAXNM */ gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); break; - case 0x1a: /* FADD */ - gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x1c: /* FCMEQ */ gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -9188,27 +9229,18 @@ static void handle_3same_float(DisasContext *s, int= size, int elements, case 0x38: /* FMINNM */ gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); break; - case 0x3a: /* FSUB */ - gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x3e: /* FMIN */ gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); break; case 0x3f: /* FRSQRTS */ gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); break; - case 0x5b: /* FMUL */ - gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x5c: /* FCMGE */ gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst); break; case 0x5d: /* FACGE */ gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst); break; - case 0x5f: /* FDIV */ - gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x7a: /* FABD */ gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); gen_helper_vfp_absd(tcg_res, tcg_res); @@ -9220,7 +9252,11 @@ static void handle_3same_float(DisasContext *s, int = size, int elements, gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); break; default: + case 0x1a: /* FADD */ case 0x1b: /* FMULX */ + case 0x3a: /* FSUB */ + case 0x5b: /* FMUL */ + case 0x5f: /* FDIV */ g_assert_not_reached(); } =20 @@ -9244,9 +9280,6 @@ static void handle_3same_float(DisasContext *s, int s= ize, int elements, gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_res, fpst); break; - case 0x1a: /* FADD */ - gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x1c: /* FCMEQ */ gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -9262,27 +9295,18 @@ static void handle_3same_float(DisasContext *s, int= size, int elements, case 0x38: /* FMINNM */ gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); break; - case 0x3a: /* FSUB */ - gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x3e: /* FMIN */ gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); break; case 0x3f: /* FRSQRTS */ gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); break; - case 0x5b: /* FMUL */ - gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x5c: /* FCMGE */ gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst); break; case 0x5d: /* FACGE */ gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst); break; - case 0x5f: /* FDIV */ - gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x7a: /* FABD */ gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); gen_helper_vfp_abss(tcg_res, tcg_res); @@ -9294,7 +9318,11 @@ static void handle_3same_float(DisasContext *s, int = size, int elements, gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); break; default: + case 0x1a: /* FADD */ case 0x1b: /* FMULX */ + case 0x3a: /* FSUB */ + case 0x5b: /* FMUL */ + case 0x5f: /* FDIV */ g_assert_not_reached(); } =20 @@ -11217,15 +11245,11 @@ static void disas_simd_3same_float(DisasContext *= s, uint32_t insn) case 0x19: /* FMLA */ case 0x39: /* FMLS */ case 0x18: /* FMAXNM */ - case 0x1a: /* FADD */ case 0x1c: /* FCMEQ */ case 0x1e: /* FMAX */ case 0x38: /* FMINNM */ - case 0x3a: /* FSUB */ case 0x3e: /* FMIN */ - case 0x5b: /* FMUL */ case 0x5c: /* FCMGE */ - case 0x5f: /* FDIV */ case 0x7a: /* FABD */ case 0x7c: /* FCMGT */ if (!fp_access_check(s)) { @@ -11255,7 +11279,11 @@ static void disas_simd_3same_float(DisasContext *s= , uint32_t insn) return; =20 default: + case 0x1a: /* FADD */ case 0x1b: /* FMULX */ + case 0x3a: /* FSUB */ + case 0x5b: /* FMUL */ + case 0x5f: /* FDIV */ unallocated_encoding(s); return; } @@ -11599,19 +11627,15 @@ static void disas_simd_three_reg_same_fp16(DisasC= ontext *s, uint32_t insn) switch (fpopcode) { case 0x0: /* FMAXNM */ case 0x1: /* FMLA */ - case 0x2: /* FADD */ case 0x4: /* FCMEQ */ case 0x6: /* FMAX */ case 0x7: /* FRECPS */ case 0x8: /* FMINNM */ case 0x9: /* FMLS */ - case 0xa: /* FSUB */ case 0xe: /* FMIN */ case 0xf: /* FRSQRTS */ - case 0x13: /* FMUL */ case 0x14: /* FCMGE */ case 0x15: /* FACGE */ - case 0x17: /* FDIV */ case 0x1a: /* FABD */ case 0x1c: /* FCMGT */ case 0x1d: /* FACGT */ @@ -11625,7 +11649,11 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) pairwise =3D true; break; default: + case 0x2: /* FADD */ case 0x3: /* FMULX */ + case 0xa: /* FSUB */ + case 0x13: /* FMUL */ + case 0x17: /* FDIV */ unallocated_encoding(s); return; } @@ -11699,9 +11727,6 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_= res, fpst); break; - case 0x2: /* FADD */ - gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x4: /* FCMEQ */ gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst= ); break; @@ -11721,27 +11746,18 @@ static void disas_simd_three_reg_same_fp16(DisasC= ontext *s, uint32_t insn) gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_= res, fpst); break; - case 0xa: /* FSUB */ - gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0xe: /* FMIN */ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); break; case 0xf: /* FRSQRTS */ gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); break; - case 0x13: /* FMUL */ - gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x14: /* FCMGE */ gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst= ); break; case 0x15: /* FACGE */ gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fps= t); break; - case 0x17: /* FDIV */ - gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); - break; case 0x1a: /* FABD */ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); @@ -11753,7 +11769,11 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fps= t); break; default: + case 0x2: /* FADD */ case 0x3: /* FMULX */ + case 0xa: /* FSUB */ + case 0x13: /* FMUL */ + case 0x17: /* FDIV */ g_assert_not_reached(); } =20 @@ -12972,7 +12992,6 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) break; case 0x01: /* FMLA */ case 0x05: /* FMLS */ - case 0x09: /* FMUL */ is_fp =3D 1; break; case 0x1d: /* SQRDMLAH */ @@ -13041,6 +13060,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) /* is_fp, but we pass tcg_env not fp_status. */ break; default: + case 0x09: /* FMUL */ case 0x19: /* FMULX */ unallocated_encoding(s); return; @@ -13262,10 +13282,8 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) read_vec_element(s, tcg_res, rd, pass, MO_64); gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, = fpst); break; - case 0x09: /* FMUL */ - gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); - break; default: + case 0x09: /* FMUL */ case 0x19: /* FMULX */ g_assert_not_reached(); } @@ -13361,24 +13379,6 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) g_assert_not_reached(); } break; - case 0x09: /* FMUL */ - switch (size) { - case 1: - if (is_scalar) { - gen_helper_advsimd_mulh(tcg_res, tcg_op, - tcg_idx, fpst); - } else { - gen_helper_advsimd_mul2h(tcg_res, tcg_op, - tcg_idx, fpst); - } - break; - case 2: - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); - break; - default: - g_assert_not_reached(); - } - break; case 0x0c: /* SQDMULH */ if (size =3D=3D 1) { gen_helper_neon_qdmulh_s16(tcg_res, tcg_env, @@ -13420,6 +13420,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } break; default: + case 0x09: /* FMUL */ case 0x19: /* FMULX */ g_assert_not_reached(); } diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 86845819236..41065363710 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -1248,6 +1248,10 @@ DO_3OP(gvec_rsqrts_nf_h, float16_rsqrts_nf, float16) DO_3OP(gvec_rsqrts_nf_s, float32_rsqrts_nf, float32) =20 #ifdef TARGET_AARCH64 +DO_3OP(gvec_fdiv_h, float16_div, float16) +DO_3OP(gvec_fdiv_s, float32_div, float32) +DO_3OP(gvec_fdiv_d, float64_div, float64) + DO_3OP(gvec_fmulx_h, helper_advsimd_mulxh, float16) DO_3OP(gvec_fmulx_s, helper_vfp_mulxs, float32) DO_3OP(gvec_fmulx_d, helper_vfp_mulxd, float64) --=20 2.34.1