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Thu, 23 May 2024 08:00:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHLhQjuaMmnqZnOhZnc8p+AieE+ED4aduMULZnVF2+HgTQfVSbKulXKBrC5G13MSFm84L+I0Q== X-Received: by 2002:a17:906:a38f:b0:a59:c23d:85d8 with SMTP id a640c23a62f3a-a6228156097mr314606466b.51.1716476454530; Thu, 23 May 2024 08:00:54 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Robert Hoo , Yongwei Ma , Babu Moger Subject: [PULL 07/23] i386/cpu: Use APIC ID info to encode cache topo in CPUID[4] Date: Thu, 23 May 2024 17:00:20 +0200 Message-ID: <20240523150036.1050011-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476654736100005 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the nearest power-of-2 integer. The nearest power-of-2 integer can be calculated by pow2ceil() or by using APIC ID offset/width (like L3 topology using 1 << die_offset [3]). But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] are associated with APIC ID. For example, in linux kernel, the field "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not matched with actual core numbers and it's calculated by: "(1 << (pkg_offset - core_offset)) - 1". Therefore the topology information of APIC ID should be preferred to calculate nearest power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26]: 1. d/i cache is shared in a core, 1 << core_offset should be used instead of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. 2. L2 cache is supposed to be shared in a core as for now, thereby 1 << core_offset should also be used instead of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be calculated with the bit width between the package and SMT levels in the APIC ID (1 << (pkg_offset - core_offset) - 1). In addition, use APIC ID bits calculations to replace "pow2ceil()" for cache_info_passthrough case. [1]: efb3934adf9e ("x86: cpu: make sure number of addressable IDs for proce= ssor cores meets the spec") [2]: d7caf13b5fcf ("x86: cpu: fixup number of addressable IDs for logical p= rocessors sharing cache") [3]: d65af288a84d ("i386: Update new x86_apicid parsing rules with die_offs= et support") Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistentl= y") Suggested-by: Robert Hoo Tested-by: Yongwei Ma Signed-off-by: Zhao Liu Tested-by: Babu Moger Message-ID: <20240424154929.1487382-7-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 50 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3c66242f6d3..f3d2b8053b2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6162,7 +6162,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, { X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); - uint32_t die_offset; uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; @@ -6234,7 +6233,18 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) = << 8) | (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); break; - case 4: + case 4: { + /* + * CPUID.04H:EAX[bits 25:14]: Maximum number of addressable IDs for + * logical processors sharing this cache. + */ + int addressable_threads_width; + /* + * CPUID.04H:EAX[bits 31:26]: Maximum number of addressable IDs for + * processor cores in the physical package. + */ + int addressable_cores_width; + /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); @@ -6246,40 +6256,59 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); int vcpus_per_socket =3D cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { + addressable_cores_width =3D apicid_pkg_offset(&topo_in= fo) - + apicid_core_offset(&topo_inf= o); + *eax &=3D ~0xFC000000; - *eax |=3D (pow2ceil(cs->nr_cores) - 1) << 26; + *eax |=3D ((1 << addressable_cores_width) - 1) << 26; } if (host_vcpus_per_cache > vcpus_per_socket) { + /* Share the cache at package level. */ + addressable_threads_width =3D apicid_pkg_offset(&topo_= info); + *eax &=3D ~0x3FFC000; - *eax |=3D (pow2ceil(vcpus_per_socket) - 1) << 14; + *eax |=3D ((1 << addressable_threads_width) - 1) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; - int apic_ids_sharing_l1 =3D cpu->l1_cache_per_core ? cs->nr_th= reads : 1; + addressable_cores_width =3D apicid_pkg_offset(&topo_info) - + apicid_core_offset(&topo_info); + switch (count) { case 0: /* L1 dcache info */ + addressable_threads_width =3D cpu->l1_cache_per_core + ? apicid_core_offset(&topo_info) + : 0; encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - apic_ids_sharing_l1, cs->nr_cores, + (1 << addressable_threads_width), + (1 << addressable_cores_width), eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ + addressable_threads_width =3D cpu->l1_cache_per_core + ? apicid_core_offset(&topo_info) + : 0; encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - apic_ids_sharing_l1, cs->nr_cores, + (1 << addressable_threads_width), + (1 << addressable_cores_width), eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + addressable_threads_width =3D apicid_core_offset(&topo_inf= o); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - cs->nr_threads, cs->nr_cores, + (1 << addressable_threads_width), + (1 << addressable_cores_width), eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { + addressable_threads_width =3D apicid_die_offset(&topo_= info); encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), cs->nr_cores, + (1 << addressable_threads_width), + (1 << addressable_cores_width), eax, ebx, ecx, edx); break; } @@ -6290,6 +6319,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } } break; + } case 5: /* MONITOR/MWAIT Leaf */ *eax =3D cpu->mwait.eax; /* Smallest monitor-line size in bytes */ --=20 2.45.1