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Thu, 23 May 2024 08:00:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH4rX1SNUxqi/sea3OI+oD5NvncjNQHTmyAwiOyekA4TG0W6l9HONHCp7am9z4InagSjIuKeg== X-Received: by 2002:a19:385c:0:b0:51e:25d2:453f with SMTP id 2adb3069b0e04-526c15eb8admr2943898e87.68.1716476439095; Thu, 23 May 2024 08:00:39 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 01/23] target/i386: generate simpler code for ROL/ROR with immediate count Date: Thu, 23 May 2024 17:00:14 +0200 Message-ID: <20240523150036.1050011-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476503808100001 Content-Type: text/plain; charset="utf-8" gen_rot_carry and gen_rot_overflow are meant to be called with count =3D=3D= NULL if the count cannot be zero. However this is not done in gen_ROL and gen_R= OR, and writing everywhere "can_be_zero ? count : NULL" is burdensome and less readable. Just pass can_be_zero as a separate argument. gen_RCL and gen_RCR use a conditional branch to skip the computation if count is zero, so they can pass false unconditionally to gen_rot_overflo= w. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson Message-ID: <20240522123914.608516-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/tcg/emit.c.inc | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 2dee33dd487..33cb59e54b8 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -2901,14 +2901,15 @@ static bool gen_eflags_adcox(DisasContext *s, X86De= codedInsn *decode, bool want_ return got_cf; } =20 -static void gen_rot_overflow(X86DecodedInsn *decode, TCGv result, TCGv old= , TCGv count) +static void gen_rot_overflow(X86DecodedInsn *decode, TCGv result, TCGv old, + bool can_be_zero, TCGv count) { MemOp ot =3D decode->op[0].ot; - TCGv temp =3D count ? tcg_temp_new() : decode->cc_src2; + TCGv temp =3D can_be_zero ? tcg_temp_new() : decode->cc_src2; =20 tcg_gen_xor_tl(temp, old, result); tcg_gen_extract_tl(temp, temp, (8 << ot) - 1, 1); - if (count) { + if (can_be_zero) { tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_src2, count, tcg_consta= nt_tl(0), decode->cc_src2, temp); } @@ -3000,7 +3001,7 @@ static void gen_RCL(DisasContext *s, CPUX86State *env= , X86DecodedInsn *decode) /* Compute result and outgoing overflow */ tcg_gen_mov_tl(decode->cc_src2, s->T0); tcg_gen_or_tl(s->T0, low, high); - gen_rot_overflow(decode, s->T0, decode->cc_src2, NULL); + gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); =20 if (zero_label) { gen_set_label(zero_label); @@ -3053,7 +3054,7 @@ static void gen_RCR(DisasContext *s, CPUX86State *env= , X86DecodedInsn *decode) /* Compute result and outgoing overflow */ tcg_gen_mov_tl(decode->cc_src2, s->T0); tcg_gen_or_tl(s->T0, low, high); - gen_rot_overflow(decode, s->T0, decode->cc_src2, NULL); + gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); =20 if (zero_label) { gen_set_label(zero_label); @@ -3129,9 +3130,10 @@ static TCGv_i32 gen_rot_replicate(MemOp ot, TCGv in) } } =20 -static void gen_rot_carry(X86DecodedInsn *decode, TCGv result, TCGv count,= int bit) +static void gen_rot_carry(X86DecodedInsn *decode, TCGv result, + bool can_be_zero, TCGv count, int bit) { - if (count =3D=3D NULL) { + if (!can_be_zero) { tcg_gen_extract_tl(decode->cc_dst, result, bit, 1); } else { TCGv temp =3D tcg_temp_new(); @@ -3165,8 +3167,8 @@ static void gen_ROL(DisasContext *s, CPUX86State *env= , X86DecodedInsn *decode) } else { tcg_gen_rotl_tl(s->T0, s->T0, count); } - gen_rot_carry(decode, s->T0, count, 0); - gen_rot_overflow(decode, s->T0, old, count); + gen_rot_carry(decode, s->T0, can_be_zero, count, 0); + gen_rot_overflow(decode, s->T0, old, can_be_zero, count); } =20 static void gen_ROR(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) @@ -3190,12 +3192,12 @@ static void gen_ROR(DisasContext *s, CPUX86State *e= nv, X86DecodedInsn *decode) tcg_gen_rotr_i32(temp32, temp32, count32); /* Zero extend to facilitate later optimization. */ tcg_gen_extu_i32_tl(s->T0, temp32); - gen_rot_carry(decode, s->T0, count, 31); + gen_rot_carry(decode, s->T0, can_be_zero, count, 31); } else { tcg_gen_rotr_tl(s->T0, s->T0, count); - gen_rot_carry(decode, s->T0, count, TARGET_LONG_BITS - 1); + gen_rot_carry(decode, s->T0, can_be_zero, count, TARGET_LONG_BITS = - 1); } - gen_rot_overflow(decode, s->T0, old, count); + gen_rot_overflow(decode, s->T0, old, can_be_zero, count); } =20 static void gen_RORX(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) --=20 2.45.1