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Thu, 23 May 2024 08:01:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEWgFAkvYU8dlsswJzloFiOybHVreP+VN+veAttkceMPmIpl/XfkHLOvMSmQyTiu2rIyJPjGw== X-Received: by 2002:a17:906:6a02:b0:a59:c319:f1e0 with SMTP id a640c23a62f3a-a6228171b37mr385429166b.75.1716476470212; Thu, 23 May 2024 08:01:10 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yongwei Ma , Zhuocheng Ding , Babu Moger Subject: [PULL 13/23] i386: Introduce module level cpu topology to CPUX86State Date: Thu, 23 May 2024 17:00:26 +0200 Message-ID: <20240523150036.1050011-14-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240523150036.1050011-1-pbonzini@redhat.com> References: <20240523150036.1050011-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1716476576245100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Intel CPUs implement module level on hybrid client products (e.g., ADL-N, MTL, etc) and E-core server products. A module contains a set of cores that share certain resources (in current products, the resource usually includes L2 cache, as well as module scoped features and MSRs). Module level support is the prerequisite for L2 cache topology on module level. With module level, we can implement the Guest's CPU topology and future cache topology to be consistent with the Host's on Intel hybrid client/E-core server platforms. Tested-by: Yongwei Ma Co-developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu Tested-by: Babu Moger Message-ID: <20240424154929.1487382-13-zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 3 +++ hw/i386/x86-common.c | 5 +++++ target/i386/cpu.c | 1 + 3 files changed, 9 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8c83900202d..e79293158a0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1898,6 +1898,9 @@ typedef struct CPUArchState { /* Number of dies within this CPU package. */ unsigned nr_dies; =20 + /* Number of modules within one die. */ + unsigned nr_modules; + /* Bitmap of available CPU topology levels for this CPU. */ DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX); } CPUX86State; diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 7d4f9b20f23..994f8424889 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -271,6 +271,11 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 init_topo_info(&topo_info, x86ms); =20 + if (ms->smp.modules > 1) { + env->nr_modules =3D ms->smp.modules; + /* TODO: Expose module level in CPUID[0x1F]. */ + } + if (ms->smp.dies > 1) { env->nr_dies =3D ms->smp.dies; set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f95d539eeff..eb1642c253c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7887,6 +7887,7 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; =20 + env->nr_modules =3D 1; env->nr_dies =3D 1; =20 /* SMT, core and package levels are set by default. */ --=20 2.45.1